System and method for un-interrupted operation of communications during interference
    3.
    发明授权
    System and method for un-interrupted operation of communications during interference 有权
    干扰期间通信中断操作的系统和方法

    公开(公告)号:US08842767B2

    公开(公告)日:2014-09-23

    申请号:US12771722

    申请日:2010-04-30

    IPC分类号: H04B15/00

    CPC分类号: H04L25/03146 H04L25/03057

    摘要: Methods and systems to substantially eliminate effects of EMI burst noise in an Ethernet system are provided herein. The method includes the step of computing and storing filter coefficients configured to adapt to a range of EMI frequencies. The method further comprises the step of receiving a signal and detecting EMI and frequency of the EMI in the received signal. The method further comprises selecting filter coefficients corresponding to the determined frequency of the detected EMI and adjusting a frequency response of one or more filters using the selected filter coefficients so as to substantially eliminate effects of the EMI in the received signal. The method further includes the step of sending filter coefficients to a link partner corresponding to the frequency of the detected EMI.

    摘要翻译: 本文提供了在以太网系统中基本上消除EMI突发噪声影响的方法和系统。 该方法包括计算和存储被配置为适应EMI频率范围的滤波器系数的步骤。 该方法还包括在接收信号中接收信号并检测EMI和频率的步骤。 该方法还包括选择与所检测的EMI的所确定的频率对应的滤波器系数,并且使用所选择的滤波器系数调整一个或多个滤波器的频率响应,以便基本上消除接收信号中EMI的影响。 该方法还包括将滤波器系数发送到对应于检测到的EMI的频率的链路伙伴的步骤。

    Data detection and decoding system and a method of detecting and decoding data
    4.
    发明授权
    Data detection and decoding system and a method of detecting and decoding data 失效
    数据检测和解码系统以及数据检测和解码方法

    公开(公告)号:US07421643B2

    公开(公告)日:2008-09-02

    申请号:US11029148

    申请日:2005-01-04

    IPC分类号: H03M13/00

    摘要: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

    摘要翻译: 一种数据检测和解码系统,其中在信道检测器中使用由编码器添加到每个码字的末尾的单个奇偶校验位,以提高在信道检测器中进行位决定的精度。 然后由解码器处理比特估计和可靠性估计以恢复原始输入比特。 通过将这种双重目的的单一奇偶校验与跟随信道检测器的解码器结合使用,并使用比特估计和可靠性估计来恢复原始输入比特,数据检测和解码系统的性能大大提高,同时克服了 已知的数字录音系统。

    Format efficient timing acquisition for magnetic recording read channels
    5.
    发明申请
    Format efficient timing acquisition for magnetic recording read channels 有权
    为磁记录读通道格式化高效的定时采集

    公开(公告)号:US20070064836A1

    公开(公告)日:2007-03-22

    申请号:US11228762

    申请日:2005-09-16

    IPC分类号: H04L27/00 H03D3/24 H04L7/00

    摘要: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

    摘要翻译: 一种使用前置码同步位的磁记录应用的定时恢复电路。 定时恢复电路使用具有数字旋转器的经修改的数字锁相环。 模数转换器(ADC)接收模拟输入,并向数字旋转器提供ADC数字采样。 为了补偿模拟延迟和回转,应注意,改变ADC中的采样点等同于在输出中引入相位变化。 例如,使用数字旋转器可以比通过改变模拟采样点更快地数字地引入该相位变化。 与改变ADC采样点所需的时间相比,数字旋转器几乎瞬间捕捉到初始相位估计。 当ADC转换到初始相位估计时,数字旋转器将逐步退化,直到ADC达到初始相位估计。

    Data detection and decoding system and a method of detecting and decoding data
    6.
    发明申请
    Data detection and decoding system and a method of detecting and decoding data 失效
    数据检测和解码系统以及数据检测和解码方法

    公开(公告)号:US20060150065A1

    公开(公告)日:2006-07-06

    申请号:US11029148

    申请日:2005-01-04

    IPC分类号: H03M13/00

    摘要: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

    摘要翻译: 一种数据检测和解码系统,其中在信道检测器中使用由编码器添加到每个码字的末尾的单个奇偶校验位,以提高在信道检测器中进行位决定的精度。 然后由解码器处理比特估计和可靠性估计以恢复原始输入比特。 通过将这种双重目的的单一奇偶校验与跟随信道检测器的解码器结合使用,并使用比特估计和可靠性估计来恢复原始输入比特,数据检测和解码系统的性能大大提高,同时克服了 已知的数字录音系统。

    Format efficient timing acquisition for magnetic recording read channels
    7.
    发明授权
    Format efficient timing acquisition for magnetic recording read channels 有权
    为磁记录读通道格式化高效的定时采集

    公开(公告)号:US07529320B2

    公开(公告)日:2009-05-05

    申请号:US11228762

    申请日:2005-09-16

    IPC分类号: H04L27/00

    摘要: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

    摘要翻译: 一种使用前置码同步位的磁记录应用的定时恢复电路。 定时恢复电路使用具有数字旋转器的经修改的数字锁相环。 模数转换器(ADC)接收模拟输入,并向数字旋转器提供ADC数字采样。 为了补偿模拟延迟和回转,应注意,改变ADC中的采样点等同于在输出中引入相位变化。 例如,使用数字旋转器可以比通过改变模拟采样点更快地数字地引入该相位变化。 与改变ADC采样点所需的时间相比,数字旋转器几乎瞬间捕捉到初始相位估计。 当ADC转换到初始相位估计时,数字旋转器将逐步退化,直到ADC达到初始相位估计。

    Timing error recovery system
    8.
    发明申请
    Timing error recovery system 审中-公开
    定时错误恢复系统

    公开(公告)号:US20050169415A1

    公开(公告)日:2005-08-04

    申请号:US11047377

    申请日:2005-01-31

    IPC分类号: H04B17/00 H04L7/02

    CPC分类号: H04L7/0054

    摘要: A timing error recovery system includes a phase locked loop that receives a continuous time input signal, samples the input signal at a sampling rate and generates a voltage control signal. A statistical estimator, such as a maximum a posteriori estimator, compares the voltage control signal with an expected error based upon a statistical model and produces an adjusted voltage control signal that drives a voltage controlled oscillator to adjust the sampling rate.

    摘要翻译: 定时误差恢复系统包括一个接收连续时间输入信号的锁相环,以采样率对输入信号进行采样并产生电压控制信号。 诸如最大后验估计器之类的统计估计器将电压控制信号与基于统计模型的期望误差进行比较,并产生调节的电压控制信号,该信号驱动压控振荡器以调整采样率。

    Conditionally input saturated Viterbi detector
    9.
    发明授权
    Conditionally input saturated Viterbi detector 有权
    有条件地输入饱和维特比检测器

    公开(公告)号:US07876862B2

    公开(公告)日:2011-01-25

    申请号:US11778177

    申请日:2007-07-16

    申请人: Hao Zhong German Feyh

    发明人: Hao Zhong German Feyh

    IPC分类号: H04L27/06 H03D1/00 H03M13/03

    摘要: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

    摘要翻译: 本发明的各种实施例提供了用于解码编码信息的系统和方法。 例如,包括分支度量计算器的解码器,其基于实际输入或饱和输入有条件地计算分支度量。 这种分支度量计算器可操作以接收实际输入,并将实际输入与预期范围进行比较。 有时,上述比较产生指示实际输入超出预期范围的比较结果。 计算与第一分支相关联的第一分支度量。 在第一分支具有表示期望范围的边界的期望值的情况下,使用饱和输入来计算第一分支度量。 此外,计算与第二分支相关联的第二分支度量。 在第二分支具有表示不同于期望范围的边界以外的其他值的期望值的情况下,使用实际输入来计算第二分支度量。

    Conditionally Input Saturated Viterbi Detector
    10.
    发明申请
    Conditionally Input Saturated Viterbi Detector 有权
    有条件输入饱和维特比检测器

    公开(公告)号:US20090022250A1

    公开(公告)日:2009-01-22

    申请号:US11778177

    申请日:2007-07-16

    申请人: Hao Zhong German Feyh

    发明人: Hao Zhong German Feyh

    IPC分类号: H04L27/06 H03D1/00 H03M13/03

    摘要: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

    摘要翻译: 本发明的各种实施例提供了用于解码编码信息的系统和方法。 例如,包括分支度量计算器的解码器,其基于实际输入或饱和输入有条件地计算分支度量。 这种分支度量计算器可操作以接收实际输入,并将实际输入与预期范围进行比较。 有时,上述比较产生指示实际输入超出预期范围的比较结果。 计算与第一分支相关联的第一分支度量。 在第一分支具有表示期望范围的边界的期望值的情况下,使用饱和输入来计算第一分支度量。 此外,计算与第二分支相关联的第二分支度量。 在第二分支具有表示不同于期望范围的边界以外的其他值的期望值的情况下,使用实际输入来计算第二分支度量。