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公开(公告)号：US06433722B1
公开(公告)日：2002-08-13
申请号：US09923706
申请日：2001-08-07
IPC分类号： H03M166
CPC分类号： H03M1/662
摘要： A circuit and method is provided that allows for communication of digital to analog data over more that one channel employing a single current switching DAC and a current switching multiplexer. The current switching multiplexer is an output stage circuit that is used to steer the current from one output channel to another. The data rate of the data transmitted to the DAC is increased by the number of channels that the data is being transmitted over. The data is then switched from one channel to the other by employing a current switching multiplexer, such that the device provides for the same functionality that conventional devices utilizing a single DAC for multiple channels as opposed to a single DAC for a single channel.
摘要翻译： 提供了一种电路和方法，其允许通过采用单电流开关DAC和电流开关多路复用器的多于一个通道的数字到模拟数据的通信。 电流开关多路复用器是用于将电流从一个输出通道转向另一个的输出级电路。 发送到DAC的数据的数据速率增加数据传输的通道数。 然后通过采用电流开关多路复用器将数据从一个通道切换到另一个通道，使得该器件提供与用于单个通道的单个DAC相反的用于多个通道的常规器件与传统器件相同的功能。
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公开(公告)号：US06922470B2
公开(公告)日：2005-07-26
申请号：US10167913
申请日：2002-06-12
CPC分类号： H04M1/738
摘要： A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line comprising a pair of wires. A digital feedback signal is subtracted from a predetermined voltage (alternately, current) limit digital value to provide a digital error signal that represents the difference between the voltage (alternately, current) limit digital value and the digital feedback signal. The digital error signal is multiplied by a predetermined digital gain value to provide a scaled digital error value. The scaled digital error value is integrated over time to generate an integrated digital error signal having a first predetermined number n of significant bits. A modified digital error signal is received, comprising a second predetermined number m of bits, where m
摘要翻译： 一种直流馈送控制器中的方法和装置，用于控制用户线路接口电路，控制包括一对导线的电话线上的电压（交替地，电流）。 从预定电压（交替地，电流）限制数字值中减去数字反馈信号，以提供表示电压（交替地，电流）限制数字值和数字反馈信号之间的差的数字误差信号。 将数字误差信号乘以预定的数字增益值以提供缩放的数字误差值。 缩放的数字误差值随时间积分以产生具有第一预定数量n的有效位的积分数字误差信号。 接收修改后的数字误差信号，包括作为输入的集成数字误差信号的m
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3.发明授权Digital integrator for pulse-density modulation using an adder carry or an integrator overflow 失效用于使用加法器进位或积分器溢出进行脉冲密度调制的数字积分器
公开(公告)号：US5995546A
公开(公告)日：1999-11-30
申请号：US941516
申请日：1997-09-30
申请人： Donald C. Richardson
发明人： Donald C. Richardson
CPC分类号： G06F7/5095 , G06F7/602
摘要： A pulse-density modulator (10) for producing a pulse density output signal on an output line (36) representing successive parallel digital input words on input terminals (12) has a plurality of full adders (14, 16, 18), each having a carry output (C), and an input (A) for receiving a respective bit of a concurrently applied bit of the parallel input digital words. The overflow output (C) of each of the adders (14, 16, 18) is added as an input (B) of an adder of a next successively higher bit order. A latch (30) receives the carry output (C) of one of the adders (14) in a most significant bit position, with an output of the latch provides a pulse density modulated signal on an output line (36) representing the input digital words. A clock (35) applies clock pulses to the latches (20, 22, 24, 30) at a frequency at least as high as the frequency at which the successive parallel digital input words are applied to the inputs (12) of the adders (14, 16, 18).
摘要翻译： 一种用于在输出线（36）上产生表示输入端子（12）上的连续并行数字输入字的脉冲密度输出信号的脉冲密度调制器（10）具有多个全加器（14,16,18），每个具有 进位输出（C）和用于接收并行输入数字字的同时施加位的相应位的输入（A）。 每个加法器（14,16,18）的溢出输出（C）作为下一个连续更高位序的加法器的输入（B）相加。 锁存器（30）在最高有效位位置接收加法器（14）之一的进位输出（C），锁存器的输出在输出线（36）上提供脉冲密度调制信号，输出线（36）表示输入数字 话。 时钟（35）以至少与连续并行数字输入字施加到加法器的输入（12）的频率一样高的频率将时钟脉冲施加到锁存器（20,22,24,30） 14，16，18）。
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公开(公告)号：US4564736A
公开(公告)日：1986-01-14
申请号：US608042
申请日：1984-05-07
CPC分类号： B23K26/0096 , B23K26/06 , B23K26/064 , B23K26/0648 , B23K26/0665 , B23K26/142 , B23K26/1476 , G02B6/4296
摘要： Laser processes such as cutting, drilling, and welding metals and other materials are performed manually with a hand held fiber optic laser tool. A near infrared or visible wavelength pulsed laser beam is coupled to the tool by a single clad quartz fiber whose ends are prepared to reduce losses and which transmits laser energy with peak powers in the kilowatt range to the output end. The hand held laser tool is comprised of focusing optics for the laser beam, an inert gas supply for welding cover gas, and an oxygen supply for gas assist cutting.
摘要翻译： 诸如切割，钻孔和焊接金属和其他材料的激光工艺是用手持光纤激光工具手动执行的。 近红外或可见波长的脉冲激光束通过单个包层石英光纤耦合到工具，其中端部被准备好以减少损耗，并将具有千瓦范围内的峰值功率的激光能量传输到输出端。 手持激光工具包括用于激光束的聚焦光学元件，用于焊接覆盖气体的惰性气体供应和用于气体辅助切割的氧供应。
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5.发明授权ADSL front-end in a low voltage process that accommodates large line voltages 有权ADSL前端处于低压工艺，可以容纳大的线路电压公开(公告)号：US06904145B2
公开(公告)日：2005-06-07
申请号：US09957955
申请日：2001-09-21
CPC分类号： H04M1/7385
摘要： The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.
摘要翻译： 非对称数字用户线路接收信道包括：耦合到电话线路24和26的第一和第二外部电阻器20和22; 在低电压工艺中形成的粗略可编程增益放大器CPGA，其具有耦合到第一和第二外部电阻器20和22的输入; 以及耦合到粗略可编程增益放大器CPGA的输出的精细可编程增益放大器PGA1，并且具有非常精细的增益调整以补偿外部电阻20和22与粗略可编程增益放大器CPGA之间的失配。
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公开(公告)号：US06897701B2
公开(公告)日：2005-05-24
申请号：US10436769
申请日：2003-05-13
CPC分类号： H03K17/063 , G05F3/262
摘要： A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.
摘要翻译： 提供了一种用于线性化MOS开关导通电阻和非线性结电容的技术。 该技术通过使用具有适当DC偏移的具有基本上单位增益的缓冲器来线性化采样开关，以驱动MOS阱的隔离体端子以改善无杂散动态范围（SFDR）。 以这种方式，诸如非线性体效应（V SUB）和非线性结电容（C SUB）的二阶效应 （V SB SB））可以基本上除去。
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公开(公告)号：US5029305A
公开(公告)日：1991-07-02
申请号：US287924
申请日：1988-12-21
申请人： Donald C. Richardson
发明人： Donald C. Richardson
CPC分类号： H03M1/0809 , H03M1/361
摘要： A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).
摘要翻译： 一种用于校正温度计代码数据阵列（32）中的错误的方法和装置。 并行A / D转换器（22）包括比较器的阵列（26）和编码器（30）。 由比较器（26）产生的数据阵列（32）中的误差校正由位于比较器阵列（26）和编码器（30）之间的多数误差校正门阵列（24）来实现， A / D转换器（22）。
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公开(公告)号：US06894548B2
公开(公告)日：2005-05-17
申请号：US10384262
申请日：2003-03-07
CPC分类号： H03K5/1565
摘要： The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.
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公开(公告)号：US06621346B1
公开(公告)日：2003-09-16
申请号：US09314764
申请日：1999-05-19
IPC分类号： H03G310
CPC分类号： H04L27/0002 , H04B3/145 , H04B3/23 , H04L5/023 , H04L25/03878
摘要： Digital subscriber modems (8, 15) for use in Asynchronous Digital Subscriber Line (ADSL) communications are disclosed. The central office modem (8) includes a digital transceiver function (10) and an analog front end function (12), where the analog front end function (12) is integrated into a single integrated circuit. According to the disclosed embodiments, the analog front end function (12) includes a transmit and a receive side. On the receive side, an impedance matching circuit (56) is coupled to the input of a programmable gain amplifier (54C). The impedance matching circuit (56) is controlled by the same control signals (C1, C2, C3) as used to select the gain of the programmable gain amplifier (54C), so that a constant input impedance is presented to the signal input (RXP), independent of the selected gain.
摘要翻译： 公开了用于异步数字用户线（ADSL）通信的数字用户调制解调器（8,15）。 中央办公室调制解调器（8）包括数字收发器功能（10）和模拟前端功能（12），其中模拟前端功能（12）被集成到单个集成电路中。 根据所公开的实施例，模拟前端功能（12）包括发送和接收侧。 在接收侧，阻抗匹配电路（56）耦合到可编程增益放大器（54C）的输入端。 阻抗匹配电路（56）由用于选择可编程增益放大器（54C）的增益的相同的控制信号（C1，C2，C3）来控制，使得恒定的输入阻抗被呈现给信号输入端 ），独立于所选增益。
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公开(公告)号：US06366230B1
公开(公告)日：2002-04-02
申请号：US09589406
申请日：2000-06-07
IPC分类号： H03M134
摘要： A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.
摘要翻译： 流水线模数转换器包括具有第一分辨率的模数转换器的第一级700。 第一级700包括三电容器开关电容器电路。 模数转换器还包括一个或多个后续的模数转换器级200.第一级和后级级700和200被流水线化在一起以提供数字输出信号。
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