公开(公告)号：US20080010580A1

公开(公告)日：2008-01-10

申请号：US11167774

申请日：2005-06-27

申请人： David Anderson ,  Sami Iren ,  Xueshi Yang

发明人： David Anderson ,  Sami Iren ,  Xueshi Yang

IPC分类号： G11C29/00

CPC分类号： G11B20/1833 ,  G11B2220/2516

摘要： A storage device comprising has a storage medium, a read-write mechanism, an object-based file system interface, and a controller. The read-write mechanism is adapted to read and to write data from and to the storage medium. The object-based file system interface within the storage device is adapted to organize and access data on the storage medium as objects and to access attributes of each data object. The controller is adapted to generate redundancy data for each data object to be stored on the storage medium according to the associated attributes and to store the data object and its associated redundancy data on the storage medium.

摘要翻译： 一种存储装置，包括存储介质，读写机构，基于对象的文件系统接口和控制器。 读写机构适于从存储介质读取和写入数据。 存储设备内的基于对象的文件系统接口适于组织和访问存储介质上的数据作为对象并访问每个数据对象的属性。 控制器适于根据相关联的属性为要存储在存储介质上的每个数据对象生成冗余数据，并将数据对象及其相关冗余数据存储在存储介质上。

公开(公告)号：US07533330B2

公开(公告)日：2009-05-12

申请号：US11167774

申请日：2005-06-27

申请人： David Anderson ,  Sami Iren ,  Xueshi Yang

发明人： David Anderson ,  Sami Iren ,  Xueshi Yang

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B2220/2516

摘要： A storage device comprising has a storage medium, a read-write mechanism, an object-based file system interface, and a controller. The read-write mechanism is adapted to read and to write data from and to the storage medium. The object-based file system interface within the storage device is adapted to organize and access data on the storage medium as objects and to access attributes of each data object. The controller is adapted to generate redundancy data for each data object to be stored on the storage medium according to the associated attributes and to store the data object and its associated redundancy data on the storage medium.

摘要翻译： 一种存储装置，包括存储介质，读写机构，基于对象的文件系统接口和控制器。 读写机构适于从存储介质读取和写入数据。 存储设备内的基于对象的文件系统接口适于组织和访问存储介质上的数据作为对象并访问每个数据对象的属性。 控制器适于根据相关联的属性为要存储在存储介质上的每个数据对象生成冗余数据，并将数据对象及其相关冗余数据存储在存储介质上。

公开(公告)号：US09048879B1

公开(公告)日：2015-06-02

申请号：US13586710

申请日：2012-08-15

申请人： Shaohua Yang ,  Zining Wu ,  Gregory Burd ,  Xueshi Yang ,  Hongwei Song ,  Nedeljko Varnica

发明人： Shaohua Yang ,  Zining Wu ,  Gregory Burd ,  Xueshi Yang ,  Hongwei Song ,  Nedeljko Varnica

IPC分类号： H03M13/29 ,  H04L1/00

CPC分类号： H03M13/2945 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/23 ,  H03M13/2909 ,  H03M13/2957 ,  H03M13/3746 ,  H04L1/0065

摘要： An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

摘要翻译： 纠错系统包括使用交织分量代码和嵌入奇偶校验分量代码的迭代代码。 在一些实施例中，在传输侧，在输入节点处接收的输入信号基于交织的代码进行编码，该代码编码输入数据的交错版本以产生第一组码字。 第一组码字的至少一部分优选地被划分为多个符号，这些符号基于嵌入的奇偶校验码被编码以提供编码数据。 类似地，在一些实施例中，在接收侧，检测所接收的数据以产生检测到的信息和软输出。 检测到的信息根据嵌入的奇偶校验码进行解码以获得解码的信息。 解码的信息优选地与其他软信息一起被交织的解码器使用以产生用于偏置随后的解码迭代的可靠性度量。

公开(公告)号：US09015562B1

公开(公告)日：2015-04-21

申请号：US12543006

申请日：2009-08-18

申请人： Shumei Song ,  Xueshi Yang

发明人： Shumei Song ,  Xueshi Yang

IPC分类号： G11B20/18 ,  G11B19/02

CPC分类号： G11B19/025 ,  G11B20/1833 ,  G11B2020/1859

摘要： In one embodiment, the present invention includes an error correction method. The error correction method comprises receiving a digital signal and processing the digital signal to perform a first error correction. The first error correction includes a first correction for data insertions or deletions and a first correction of data errors to generate a reference signal. The reference signal corresponds to the digital signal having been corrected to a first correction accuracy. The digital signal and the reference signal may be processed to perform a second correction for data insertions or deletions to generate a synchronized signal. The second correction of the digital signal is based on the reference signal, and the correction accuracy of the second correction is more accurate than the first correction accuracy.

摘要翻译： 在一个实施例中，本发明包括纠错方法。 误差校正方法包括接收数字信号并处理数字信号以执行第一纠错。 第一纠错包括用于数据插入或删除的第一校正以及数据错误的第一校正以产生参考信号。 参考信号对应于已被校正为第一校正精度的数字信号。 数字信号和参考信号可以被处理以执行用于数据插入或删除的第二校正以产生同步信号。 数字信号的第二校正基于参考信号，并且第二校正的校正精度比第一校正精度更准确。

公开(公告)号：US08635508B2

公开(公告)日：2014-01-21

申请号：US13604391

申请日：2012-09-05

申请人： Xueshi Yang ,  Zining Wu ,  Seo-How Low

发明人： Xueshi Yang ,  Zining Wu ,  Seo-How Low

IPC分类号： H03M13/00

CPC分类号： H03M13/2927 ,  G06F11/1072 ,  H03M13/152 ,  H03M13/2903 ,  H03M13/2906

摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.

摘要翻译： 提供了一种用于执行串联纠错的系统和方法。 在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有 第一个逻辑单元。 该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

公开(公告)号：US08611151B1

公开(公告)日：2013-12-17

申请号：US13268183

申请日：2011-10-07

申请人： Xueshi Yang

发明人： Xueshi Yang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C7/10

CPC分类号： G11C16/0483 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/26 ,  G11C16/28 ,  G11C16/344 ,  G11C2211/5634 ,  G11C2216/16

摘要： This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.

公开(公告)号：US08437193B1

公开(公告)日：2013-05-07

申请号：US12820266

申请日：2010-06-22

申请人： Xueshi Yang

发明人： Xueshi Yang

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C16/349

摘要： An apparatus and method for selectively controlling application of a data recovery bias voltage are described. One example apparatus includes replenish logic configured to selectively control application of a data recovery bias voltage to a control gate associated with a cell in a flash memory apparatus. The replenish logic may be configured to select the data recovery bias voltage to replenish charge lost from a floating gate in the flash memory apparatus. The replenish logic may also be configured to control application of the data recovery bias voltage for a period of time sufficient to charge a threshold voltage (Vt) in the cell. In one embodiment, the data recovery bias voltage is based on a program voltage employed to program a value into the cell.

摘要翻译： 描述了用于选择性地控制数据恢复偏置电压的应用的装置和方法。 一个示例性设备包括补充逻辑，其被配置为选择性地控制数据恢复偏置电压到与闪存设备中的单元相关联的控制门的应用。 补充逻辑可以被配置为选择数据恢复偏置电压以补充从闪存设备中的浮动栅极丢失的电荷。 补充逻辑还可以被配置为控制数据恢复偏置电压的施加足以对单元中的阈值电压（Vt）充电的时间段。 在一个实施例中，数据恢复偏置电压基于用于将值编程到单元中的编程电压。

公开(公告)号：US08416623B2

公开(公告)日：2013-04-09

申请号：US13447789

申请日：2012-04-16

申请人： Xueshi Yang

发明人： Xueshi Yang

IPC分类号： G11C11/34

CPC分类号： G11C16/28 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  H01L27/115

摘要： A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages.

摘要翻译： 系统包括电压发生器和参考电压设定模块。 电压发生器被配置为产生要施加到存储器单元的K电压。 K电压用于确定用于读取存储器单元的参考电压，其中K是大于1的整数。参考电压设置模块被配置为选择性地将参考电压设置为K个电压中的两个相邻电压之间的值 或K个电压中的两个相邻的电压之一。

公开(公告)号：US08406048B2

公开(公告)日：2013-03-26

申请号：US12535987

申请日：2009-08-05

申请人： Xueshi Yang ,  Zining Wu

发明人： Xueshi Yang ,  Zining Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/28 ,  G11C2211/5634

摘要： Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results.

摘要翻译： 描述了使用分数参考电压访问存储器的设备，系统，方法和其他实施例。 在一个实施例中，一种装置包括比较逻辑。 比较逻辑将存储器单元的阈值电压与至少一对分数参考电压进行比较以产生比较结果。 该装置包括至少部分地基于比较结果来确定存储器单元的位值的读取逻辑。

公开(公告)号：US08363478B1

公开(公告)日：2013-01-29

申请号：US13017430

申请日：2011-01-31

申请人： Xueshi Yang ,  Gregory Burd

发明人： Xueshi Yang ,  Gregory Burd

IPC分类号： G11C11/34 ,  G11C6/04

CPC分类号： G11C16/26 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/349 ,  G11C29/028 ,  G11C2211/5634

摘要： Apparatuses, methods, and other embodiments associated with group based read reference voltage management in flash memory are described. According to one embodiment, an apparatus includes an interval logic configured to create a finite set of timer intervals, a partition logic configured to selectively assign a Vref value to a set of flash memory cells as a function of a given timer interval during which the set of flash memory cells are programmed, and an adaptation logic configured to selectively adapt a given Vref value associated with a flash memory cell upon determining that the flash memory cell has been read.

摘要翻译： 描述了与闪存中的基于组的读取参考电压管理相关联的装置，方法和其它实施例。 根据一个实施例，一种装置包括间隔逻辑，其被配置为创建有限的一组定时器间隔，分区逻辑被配置为根据给定的定时器间隔来选择性地将一个Vref值分配给一组闪存单元， 闪存单元被编程，并且适配逻辑被配置为在确定闪存单元已经被读取之后选择性地调整与闪存单元相关联的给定Vref值。