公开(公告)号：US5276955A

公开(公告)日：1994-01-11

申请号：US868531

申请日：1992-04-14

申请人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

发明人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

IPC分类号： H01L21/48 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

CPC分类号： H05K3/462 ,  H01L21/4857 ,  H05K3/368 ,  H05K1/0272 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0278 ,  H05K3/325 ,  H05K3/328 ,  H05K3/4623 ,  Y10T29/49004 ,  Y10T29/49128

摘要： A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

摘要翻译： 用于制造用于电子基板和电路板的大面积多层互连的方法和装置使用由固态扩散产生的高密度区域阵列互连。 两个或更多个预测试的子部分电连接和机械连接在一起，以同时形成多层基板，而不采用流动型连接，其中导电互连材料在接合过程中的某一点处完全处于液相。 每个衬底由具有多个导电层的平面电介质衬底组成。 在衬底的至少一个表面上形成具有多个互连衬垫的导电衬垫。 互连焊盘位于电介质基板的表面上方的均匀高度处，并且包括基底金属层，具有至少一个导电焊盘层的顶部金属层具有设置在顶部金属层顶部的施主金属。 当两个或更多个子部分的导电焊盘层对准并堆叠在一起时，可以使用固态扩散将互连焊盘机械地和电连接在一起，以连接施主金属层和顶部金属层，以形成区域阵列互连，而不粘合 周围电介质基板。

公开(公告)号：US5966593A

公开(公告)日：1999-10-12

申请号：US748112

申请日：1996-11-08

申请人： John J. Budnaitis ,  Jimmy Leong

发明人： John J. Budnaitis ,  Jimmy Leong

IPC分类号： G01R31/26 ,  G01R1/06 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  H01L23/32 ,  H01L23/498 ,  H01L21/44

CPC分类号： H01L23/49827 ,  G01R1/07314 ,  G01R1/06755 ,  G01R31/2863 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49144

摘要： The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

摘要翻译： 本发明涉及一种用于对半导体晶片执行可靠性筛选的系统和方法，特别涉及用于包括晶片级老化（WLBI），切割模具老化（DDBI）， 和封装模具老化（PDBI）。 老化系统包括具有平面基座的老化基板，临时的Z轴连接构件和彼此电耦合的Z轴晶片级接触片，用于筛选晶片，切割的裸片和封装的电子部件， 他们的组装和使用。

公开(公告)号：US5966022A

公开(公告)日：1999-10-12

申请号：US748517

申请日：1996-11-08

申请人： John J. Budnaitis ,  Jimmy Leong

发明人： John J. Budnaitis ,  Jimmy Leong

IPC分类号： G01R31/26 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/326 ,  H01L21/66

CPC分类号： G01R31/2865 ,  G01R1/07314 ,  G01R1/06761 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863

摘要： The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

摘要翻译： 本发明涉及一种用于对半导体晶片执行可靠性筛选的系统和方法，特别涉及用于包括晶片级老化（WLBI），切割模具老化（DDBI）， 和封装模具老化（PDBI）。 老化系统包括具有平面基座的老化基板，临时的Z轴连接构件和彼此电耦合的Z轴晶片级接触片，用于筛选晶片，切割的裸片和封装的电子部件， 他们的组装和使用。

公开(公告)号：US5896038A

公开(公告)日：1999-04-20

申请号：US747168

申请日：1996-11-08

申请人： John J. Budnaitis ,  Jimmy Leong

发明人： John J. Budnaitis ,  Jimmy Leong

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/2863

摘要： The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

摘要翻译： 本发明涉及一种用于对半导体晶片执行可靠性筛选的系统和方法，特别涉及用于包括晶片级老化（WLBI），切割模具老化（DDBI）， 和封装模具老化（PDBI）。 老化系统包括具有平面基座的老化基板，临时的Z轴连接构件和彼此电耦合的Z轴晶片级接触片，用于筛选晶片，切割的裸片和封装的电子部件， 他们的组装和使用。