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    Method of forming redundant signal traces and corresponding electronic components
    1.
    发明授权
    Method of forming redundant signal traces and corresponding electronic components 失效
    形成冗余信号迹线和相应电子元件的方法

    公开(公告)号：US5976974A

    公开(公告)日：1999-11-02

    申请号：US847374

    申请日：1997-04-22

    申请人： Paul J. Fischer ,  Robin E. Gorrell

    发明人： Paul J. Fischer ,  Robin E. Gorrell

    IPC分类号： H01L21/48 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42 ,  H01L21/44

    CPC分类号： H05K1/0265 ,  H01L21/4846 ,  H05K3/062 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/1394 ,  H05K3/0094 ,  H05K3/064 ,  H05K3/427

    摘要： In a method for forming redundant signal traces and corresponding electronic components, a photoresist pattern which defines a semi-additive signal image is coated on at least one first conductive layer of a composite base substrate. A barrier layer of etch-resistant metal is deposited on the first conductive layer. The photoresist is removed, thereby forming a first barrier signal trace having a first line width. Optionally, one or more vias may be formed in the substrate. A surface conductive layer is deposited on the first conductive layer, the barrier layer, and on a surface of the optional vias. A photoresist pattern is coated on the surface conductive layer which defines a subtractive signal image. Predetermined portions of the surface conductive layer and the first conductive layer are removed. The photoresist is removed forming a second signal trace in overlying relationship with the first barrier signal trace and having a second line width greater than the first line width.

    摘要翻译： 在用于形成冗余信号迹线和相应的电子部件的方法中，限定半附加信号图像的光致抗蚀剂图案涂覆在复合基底基板的至少一个第一导电层上。 在第一导电层上沉积抗蚀金属的阻挡层。 去除光致抗蚀剂，从而形成具有第一线宽的第一势垒信号迹线。 可选地，可以在衬底中形成一个或多个通孔。 表面导电层沉积在第一导电层，阻挡层上以及可选通路的表面上。 在限定消减信号图像的表面导电层上涂覆光致抗蚀剂图案。 除去表面导电层和第一导电层的预定部分。 除去光致抗蚀剂，形成与第一势垒信号迹线相重叠的第二信号迹线，并具有大于第一线宽的第二线宽。

    Method of forming raised metallic contacts on electrical circuits
    2.
    发明授权
    Method of forming raised metallic contacts on electrical circuits 失效
    在电路上形成凸起的金属触点的方法

    公开(公告)号：US5747358A

    公开(公告)日：1998-05-05

    申请号：US655017

    申请日：1996-05-29

    申请人： Robin E. Gorrell ,  Paul J. Fischer

    发明人： Robin E. Gorrell ,  Paul J. Fischer

    IPC分类号： H05K3/34 ,  H01L21/60 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  H01L21/44

    CPC分类号： H05K3/4007 ,  H01L2924/0002 ,  H05K2201/0367 ,  H05K2203/0338 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4644 ,  Y10S438/977 ,  Y10T29/49126

    摘要： A method is provided for forming at least one raised metallic contact on an electrical circuit. Generally, this method includes the following steps: providing a composite base substrate which is defined by at least a first conductive layer, a dielectric material and a second conductive layer; removing a portion of the first conductive layer to expose the dielectric material; removing the exposed portion of the dielectric material to the second conductive layer, thereby forming a depression; depositing at least one layer of conductive material on at least side wall portions of the depression; removing the second conductive layer; and completely removing the dielectric material to said first conductive layer thereby forming a raised metallic contact which extends perpendicularly away from the first conductive layer.

    摘要翻译： 提供一种用于在电路上形成至少一个凸起的金属接触件的方法。 通常，该方法包括以下步骤：提供由至少第一导电层，电介质材料和第二导电层限定的复合基底基板; 去除所述第一导电层的一部分以暴露所述电介质材料; 将所述电介质材料的暴露部分移除到所述第二导电层，从而形成凹陷; 在所述凹陷的至少侧壁部分上沉积至少一层导电材料; 去除所述第二导电层; 并且将所述介电材料完全去除到所述第一导电层，从而形成垂直于所述第一导电层延伸的凸起金属接触。

    Dimensionally stable core for use in high density chip packages
    3.
    发明授权
    Dimensionally stable core for use in high density chip packages 失效
    尺寸稳定的核心用于高密度芯片封装

    公开(公告)号：US5847327A

    公开(公告)日：1998-12-08

    申请号：US747169

    申请日：1996-11-08

    申请人： Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

    发明人： Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

    IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K3/32 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46 ,  H05K1/00

    CPC分类号： H01L23/49827 ,  H05K3/445 ,  H05K3/4641 ,  H01L2924/0002 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09536 ,  H05K3/323 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4608 ,  H05K3/4614 ,  Y10T428/24917 ,  Y10T428/249958 ,  Y10T442/3415

    摘要： A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

    摘要翻译： 提供了用于高密度芯片封装的尺寸稳定的芯。 稳定的芯是具有在其中形成间隙的金属芯，优选铜。 电介质层同时设置在金属芯的顶表面和底表面上。 金属盖层同时设置在电介质层的顶表面上。 然后通过金属盖层钻出盲孔或通孔，并延伸到形成在金属芯中的电介质层和间隙中。 如果提供隔离的金属芯，则通孔不延伸穿过铜芯中的间隙。 稳定的芯材可降低基板的材料运动，并在芯片封装的层压处理期间实现从基板到基板的均匀收缩。 这允许每个基板执行相同的操作。 此外，具有尺寸稳定的芯的多个芯片封装可以结合在一起以获得高密度芯片封装。

    Method of forming raised metallic contacts on electrical circuits for permanent bonding
    4.
    发明授权
    Method of forming raised metallic contacts on electrical circuits for permanent bonding 失效
    在永久性接合的电路上形成凸起的金属触点的方法

    公开(公告)号：US5786270A

    公开(公告)日：1998-07-28

    申请号：US744842

    申请日：1996-11-08

    申请人： Robin E. Gorrell ,  Paul J. Fischer

    发明人： Robin E. Gorrell ,  Paul J. Fischer

    IPC分类号： H05K3/34 ,  H01L21/60 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  H01L21/44 ,  H01L21/463

    CPC分类号： H05K3/4007 ,  H01L2924/0002 ,  H05K2201/0367 ,  H05K2203/0338 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4644 ,  Y10S438/977 ,  Y10T29/49126

    摘要： A method is provided for forming at least one raised metallic contact on an electrical circuit for permanent bonding. Generally, this method includes the following steps: providing a composite base substrate which is defined by at least a first conductive layer, a dielectric material and a second conductive layer; removing a portion of the first conductive layer to expose the dielectric material; removing the exposed portion of the dielectric material to the second conductive layer, thereby forming a depression; depositing at least one layer of solder on at least side wall portions of the depression; depositing at least one layer of copper; removing the second conductive layer; and completely removing the dielectric material to said first conductive layer thereby forming a raised solder contact which extends perpendicularly away from the first conductive layer.

    摘要翻译： 提供一种用于在电路上形成至少一个凸起的金属接触件用于永久接合的方法。 通常，该方法包括以下步骤：提供由至少第一导电层，电介质材料和第二导电层限定的复合基底基板; 去除所述第一导电层的一部分以暴露所述电介质材料; 将所述电介质材料的暴露部分移除到所述第二导电层，从而形成凹陷; 在凹陷的至少侧壁部分上沉积至少一层焊料; 沉积至少一层铜; 去除所述第二导电层; 并且将所述介电材料完全去除到所述第一导电层，从而形成垂直于所述第一导电层延伸的凸起的焊料接触。

    Multilayer interconnect system for an area array interconnection using solid state diffusion
    7.
    发明授权
    Multilayer interconnect system for an area array interconnection using solid state diffusion 失效
    用于使用固态扩散的区域阵列互连的多层互连系统

    公开(公告)号：US5276955A

    公开(公告)日：1994-01-11

    申请号：US868531

    申请日：1992-04-14

    申请人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

    发明人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

    IPC分类号： H01L21/48 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

    CPC分类号： H05K3/462 ,  H01L21/4857 ,  H05K3/368 ,  H05K1/0272 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0278 ,  H05K3/325 ,  H05K3/328 ,  H05K3/4623 ,  Y10T29/49004 ,  Y10T29/49128

    摘要： A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

    摘要翻译： 用于制造用于电子基板和电路板的大面积多层互连的方法和装置使用由固态扩散产生的高密度区域阵列互连。 两个或更多个预测试的子部分电连接和机械连接在一起，以同时形成多层基板，而不采用流动型连接，其中导电互连材料在接合过程中的某一点处完全处于液相。 每个衬底由具有多个导电层的平面电介质衬底组成。 在衬底的至少一个表面上形成具有多个互连衬垫的导电衬垫。 互连焊盘位于电介质基板的表面上方的均匀高度处，并且包括基底金属层，具有至少一个导电焊盘层的顶部金属层具有设置在顶部金属层顶部的施主金属。 当两个或更多个子部分的导电焊盘层对准并堆叠在一起时，可以使用固态扩散将互连焊盘机械地和电连接在一起，以连接施主金属层和顶部金属层，以形成区域阵列互连，而不粘合 周围电介质基板。

    Dimensionally stable core for use in high density chip packages and a method of fabricating same
    8.
    发明授权
    Dimensionally stable core for use in high density chip packages and a method of fabricating same 有权
    用于高密度芯片封装的尺寸稳定的芯体及其制造方法

    公开(公告)号：US06344371B2

    公开(公告)日：2002-02-05

    申请号：US09136201

    申请日：1998-08-19

    申请人： Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

    发明人： Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

    IPC分类号： H01L2144

    CPC分类号： H01L23/49827 ,  H01L2924/0002 ,  H05K3/323 ,  H05K3/427 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09536 ,  Y10T428/24917 ,  Y10T428/249958 ,  Y10T442/3415 ,  H01L2924/00

    摘要： A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

    摘要翻译： 提供了用于高密度芯片封装的尺寸稳定的芯。 稳定的芯是具有在其中形成间隙的金属芯，优选铜。 电介质层同时设置在金属芯的顶表面和底表面上。 金属盖层同时设置在电介质层的顶表面上。 然后通过金属盖层钻出盲孔或通孔，并延伸到形成在金属芯中的电介质层和间隙中。 如果提供隔离的金属芯，则通孔不延伸穿过铜芯中的间隙。 稳定的芯材可降低基板的材料运动，并在芯片封装的层压处理期间实现从基板到基板的均匀收缩。 这允许每个基板执行相同的操作。 此外，具有尺寸稳定的芯的多个芯片封装可以结合在一起以获得高密度芯片封装。