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公开(公告)号：US06350673B1
公开(公告)日：2002-02-26
申请号：US09373215
申请日：1999-08-12
IPC分类号： H01L214763
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/28176 , H01L21/3003 , H01L21/31051 , H01L21/3124 , H01L21/31612 , H01L21/324 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L29/51 , Y10S438/958
摘要： A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device (10) having at least one metal layer (28) completed. Then, a planarizing dielectric layer (30) is added to the semiconductor device (10). The semiconductor device (10) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device (10).
摘要翻译： 提供了降低CHC降解的方法。 该方法包括提供具有完成的至少一个金属层（28）的半导体器件（10）。 然后，将平坦化介电层（30）加入到半导体器件（10）中。 半导体器件（10）在富含氢气的环境中被加热，直到氢完全饱和半导体器件（10）。
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公开(公告)号：US5922619A
公开(公告)日：1999-07-13
申请号：US942503
申请日：1997-10-02
申请人： David L. Larkin
发明人： David L. Larkin
IPC分类号： H01L21/336 , H01L20/21
CPC分类号： H01L29/66825
摘要： A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.
摘要翻译： 在具有多个凸起场氧化物隔离结构的硅晶片上形成浮栅的无图案自对准方法。 本发明的方法包括将多晶硅层沉积到硅晶片和凸起的场氧化物隔离结构上，在多晶硅层上沉积多晶硅蚀刻掩模层，以及平坦化多晶硅蚀刻掩模层。 然后蚀刻多晶硅蚀刻掩模层以在凸起的场氧化物隔离结构上暴露多晶硅层。 然后蚀刻暴露的多晶硅层以在凸起的场氧化物隔离结构上去除多晶硅层。 然后去除剩余的多晶硅蚀刻掩模层，留下在场氧化物隔离结构之间覆盖硅晶片的多个多晶硅区域。
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3.发明申请公开(公告)号：US20120142164A1
公开(公告)日：2012-06-07
申请号：US13396159
申请日：2012-02-14
IPC分类号： H01L21/02
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).
摘要翻译： 本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。 集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分 绝缘体（130）包括层间介电层（135,138,143或148）。 集成高压电容器还包括至少部分位于绝缘体（130）内的电容均匀性结构（910）和位于绝缘体（130）上方的第二电容器板（160）。
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4.发明授权公开(公告)号：US07470991B2
公开(公告)日：2008-12-30
申请号：US11250047
申请日：2005-10-13
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).
摘要翻译： 本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。 集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分 绝缘体（130）包括层间介电层（135,138,143或148）。 集成高压电容器还包括至少部分位于绝缘体（130）内的电容均匀性结构（910）和位于绝缘体（130）上方的第二电容器板（160）。
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5.发明授权公开(公告)号：US08273623B2
公开(公告)日：2012-09-25
申请号：US13396159
申请日：2012-02-14
IPC分类号： H01L21/8242
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).
摘要翻译： 本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。 集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分 绝缘体（130）包括层间介电层（135,138,143或148）。 集成高压电容器还包括至少部分位于绝缘体（130）内的电容均匀性结构（910）和位于绝缘体（130）上方的第二电容器板（160）。
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公开(公告)号：US08114731B2
公开(公告)日：2012-02-14
申请号：US12276507
申请日：2008-11-24
IPC分类号： H01L21/8244
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).
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7.发明授权公开(公告)号：US07413947B2
公开(公告)日：2008-08-19
申请号：US11333222
申请日：2006-01-17
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L21/02118 , H01L21/02131 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/312 , H01L27/0629 , H01L27/0805 , H01L29/94
摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130) and a top-level dielectric layer (199) located at least partially along a sidewall of the second capacitor plate (160).
摘要翻译： 本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。 集成的高压电容器以及其他特征包括位于基板（105）上方或基板（105）上的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分 绝缘体（130）包括层间电介质层（135,138,143或148）。 集成的高压电容器还包括位于绝缘体（130）上的第二电容器板（160）和至少部分地沿着第二电容器板（160）的侧壁定位的顶级介质层（199）。
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