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1.发明申请TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开具有仅一个方向的横向延伸的TRENCH电容器及相关方法公开(公告)号：US20070267671A1
公开(公告)日：2007-11-22
申请号：US11383861
申请日：2006-05-17
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.
摘要翻译： 公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。 在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。 横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。
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公开(公告)号：US20090072355A1
公开(公告)日：2009-03-19
申请号：US11856260
申请日：2007-09-17
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/76229 , H01L21/76232
摘要： A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.
摘要翻译： 在具有直的侧壁的第一浅沟槽上形成保护电介质层，同时暴露第二浅沟槽。 在半导体衬底上形成氧化阻挡层。 抗蚀剂被施加并凹入第二浅沟槽内。 在凹陷的抗蚀剂上方去除氧化阻挡层。 去除抗蚀剂并进行热氧化，使得在剩余的氧化掩模层上方形成热氧化物环。 之后除去氧化阻挡层，并对其下方的暴露的半导体区域进行蚀刻以形成瓶状浅沟槽。 第一和瓶形沟槽填充有电介质材料，分别形成直的侧壁浅沟槽隔离结构和瓶浅沟槽隔离结构。 可以使用浅沟槽隔离结构来为具有不同深度的半导体器件提供最佳的电隔离和器件性能。
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公开(公告)号：US07705386B2
公开(公告)日：2010-04-27
申请号：US11969989
申请日：2008-01-07
IPC分类号： H01L27/108 , H01L21/8244
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。
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4.发明授权公开(公告)号：US07923815B2
公开(公告)日：2011-04-12
申请号：US11969986
申请日：2008-01-07
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。
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公开(公告)号：US20090174031A1
公开(公告)日：2009-07-09
申请号：US11969986
申请日：2008-01-07
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。
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公开(公告)号：US20090173980A1
公开(公告)日：2009-07-09
申请号：US11969989
申请日：2008-01-07
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。
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公开(公告)号：US20100207245A1
公开(公告)日：2010-08-19
申请号：US12689501
申请日：2010-01-19
CPC分类号： H01L28/40 , H01L21/7682 , H01L21/76831 , H01L27/10861 , H01L29/66181
摘要： An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
摘要翻译： 公开了一种改进的沟槽结构及其制造方法。 本发明的实施例提供了一种沟槽，其中套环部分具有气隙而不是固体氧化物套环。 气隙提供较低的介电常数。 因此，本发明的实施例可以用于制造更高性能的装置（由于减小的寄生泄漏）或更小的装置，这是由于能够使用更薄的套环来获得与仅由氧化物构成的更厚的套圈相同的性能 没有气隙）。 或者，根据应用，可以进行设计选择以实现改进的性能和减小的尺寸的组合。
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8.发明授权Device structure, layout and fabrication method for uniaxially strained transistors 有权单轴应变晶体管的器件结构，布局和制造方法公开(公告)号：US08933515B2
公开(公告)日：2015-01-13
申请号：US13531175
申请日：2012-06-22
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。
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公开(公告)号：US08492817B2
公开(公告)日：2013-07-23
申请号：US12689501
申请日：2010-01-19
CPC分类号： H01L28/40 , H01L21/7682 , H01L21/76831 , H01L27/10861 , H01L29/66181
摘要： An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
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10.发明授权公开(公告)号：US08420464B2
公开(公告)日：2013-04-16
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译： 一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁 结构体。 在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。 还描述了通过上述方法形成的结构。
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