Methods and apparatus for 3D printing
    2.
    发明申请
    Methods and apparatus for 3D printing 审中-公开
    3D打印方法和设备

    公开(公告)号:US20050280185A1

    公开(公告)日:2005-12-22

    申请号:US11097987

    申请日:2005-04-01

    IPC分类号: B28B7/46 B29C41/02 B29C67/00

    摘要: The invention relates to methods and apparatus for fabricating a three-dimensional object from a representation of the object stored in memory. The apparatus includes a stationary build table for receiving successive layers of a build material and at least one movable printhead disposed above the build table. The printhead deposits a binding material in a predetermined pattern on each successive layer of the build material to form the three-dimensional object.

    摘要翻译: 本发明涉及从存储在存储器中的对象的表示来制造三维物体的方法和装置。 该装置包括用于接收构建材料的连续层的静止构建工作台和布置在构建工作台上方的至少一个可移动打印头。 打印头在构建材料的每个连续层上以预定图案沉积粘合材料以形成三维物体。

    Device fabrication by ink-jet printing materials into bank structures, and embossing tool
    6.
    发明授权
    Device fabrication by ink-jet printing materials into bank structures, and embossing tool 有权
    通过喷墨印刷材料制成银行结构的装置和压花工具

    公开(公告)号:US08372731B2

    公开(公告)日:2013-02-12

    申请号:US11714098

    申请日:2007-03-06

    IPC分类号: H01L21/20

    摘要: The invention disclosed relates to the fabrication of electronic devices. A method for fabricating an electronic device is disclosed, comprising embossing a surface of a work-piece 200, 202 using an embossing tool 204, so as to form a microstructure having at least two levels of thickness contrast on the work-piece surface, and depositing fluid 208 containing a functional material onto the microstructure. In a preferred embodiment, the step of depositing fluid 208 comprises ink-jet printing. An embossing tool 204 for creating a microstructure on a work-piece 200, 202 is also disclosed, the embossing tool 204 comprising a first surface and steps of at least two different heights relative to the first surface.

    摘要翻译: 所公开的发明涉及电子设备的制造。 公开了一种用于制造电子装置的方法,包括使用压花工具204对工件200,202的表面进行压花,以形成在工件表面上具有至少两层厚度对比度的微结构,以及 将含有功能材料的流体208沉积到微结构上。 在优选实施例中,沉积流体208的步骤包括喷墨打印。 还公开了用于在工件200,202上形成微结构的压花工具204,压花工具204包括第一表面和相对于第一表面的至少两个不同高度的台阶。

    Semiconductor film comprising discrete domains of an organic semiconductor and a method of its fabrication
    7.
    发明授权
    Semiconductor film comprising discrete domains of an organic semiconductor and a method of its fabrication 有权
    包括有机半导体的离散畴的半导体膜及其制造方法

    公开(公告)号:US07846764B2

    公开(公告)日:2010-12-07

    申请号:US11517449

    申请日:2006-09-08

    IPC分类号: H01L51/40 C30B29/54

    摘要: According to a first aspect, the present invention provides a method for forming a semiconductor film comprising a first step of providing a solution comprising a first organic semiconductor and a second organic semiconductor on a surface of a substrate. The solution is then dried to form the semiconductor film so that it comprises discrete domains of the first organic semiconductor in a matrix of the second organic semiconductor which electrically connects adjacent domains of the first organic semiconductor. The first and second semiconductors are of the same conductivity type. The mobility of charge carriers in the domains of the first organic semiconductor is higher than the mobility of charge carriers in the matrix of the second organic semiconductor. In alternative aspects, the present invention provides methods forming similar semiconductor film products but in which a solution of the first organic semiconductor is deposited separately from the second organic semiconductor and dried to form discrete domains. The present invention also provides a semiconductor film such as produced by the above methods in which both the first and second organic semiconductors are thiophenes.

    摘要翻译: 根据第一方面,本发明提供了一种形成半导体膜的方法,其包括在衬底的表面上提供包含第一有机半导体和第二有机半导体的溶液的第一步骤。 然后将溶液干燥以形成半导体膜,使得其包含第一有机半导体的第一有机半导体的相邻区域中的第二有机半导体的矩阵中的离散区域。 第一和第二半导体具有相同的导电类型。 第一有机半导体的区域中的载流子的迁移率高于第二有机半导体的基体中的电荷载流子的迁移率。 在替代方案中,本发明提供了形成类似的半导体膜产品的方法,但是其中第一有机半导体的溶液与第二有机半导体分开沉积并干燥以形成离散的畴。 本发明还提供了通过上述方法制备的半导体膜,其中第一和第二有机半导体都是噻吩。

    Self-aligning patterning method
    9.
    发明授权
    Self-aligning patterning method 失效
    自对准图案化方法

    公开(公告)号:US07390752B2

    公开(公告)日:2008-06-24

    申请号:US11253756

    申请日:2005-10-20

    IPC分类号: H01L21/302

    摘要: The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate.The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layer 16 and the conductive layer 14 thereby leaving voids. A layer of dielectric 22 is then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areas 28 of the sacrificial layer. Conductive material 30 is then deposited on the surface of the etched dielectric. Finally, the remaining areas 28 of the sacrificial layer are removed together with any overlying material.The resulting plurality of multi-layer thin film transistors is preferably in the form of an array which may in turn be formed into a display device by coupling each transistor in the array to a light-emitting cell.

    摘要翻译: 本发明涉及可用于在基板上制造多个多层薄膜晶体管的自对准图案化方法。 该方法包括首先在牺牲层18的表面上形成图案化掩模20,牺牲层18是多层结构10的一部分,其包括基底12,导电层14,绝缘层16和牺牲层18。 然后蚀刻未图案化的区域以去除牺牲层,绝缘层16和导电层14的相应区域,从而留下空隙。 然后将一层电介质22沉积在蚀刻的多层结构上以至少基本上填充空隙。 然后蚀刻沉积的电介质以便至少部分地暴露牺牲层的剩余区域28的侧面。 然后将导电材料30沉积在蚀刻的电介质的表面上。 最后,牺牲层的剩余区域28与任何上覆材料一起被去除。 所得到的多个多层薄膜晶体管优选地是阵列的形式,其可以通过将阵列中的每个晶体管耦合到发光单元而依次形成为显示装置。