公开(公告)号：US08283217B2

公开(公告)日：2012-10-09

申请号：US12717439

申请日：2010-03-04

申请人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

发明人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/762 ,  H01L27/12

摘要： A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing.

摘要翻译： 形成鳍状场效应晶体管（finFET）器件的方法包括在掩埋氧化物（BOX）层上形成多个半导体鳍片; 进行氮注入，以在与多个半导体翅片之间的区域对应的BOX层的上部形成氮化区域; 在所述半导体散热片和所述BOX层的上部的氮化区域上形成栅介电层; 以及在所述栅极介电层上形成一个或多个栅电极材料; 其中BOX层的上部的氮化区域的存在防止了作为热处理的结果，氧吸附到栅介质层中。

公开(公告)号：US20110215405A1

公开(公告)日：2011-09-08

申请号：US12717439

申请日：2010-03-04

申请人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

发明人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/762 ,  H01L27/12

摘要： A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing.

摘要翻译： 形成鳍状场效应晶体管（finFET）器件的方法包括在掩埋氧化物（BOX）层上形成多个半导体鳍片; 进行氮注入，以在与多个半导体翅片之间的区域对应的BOX层的上部形成氮化区域; 在所述半导体散热片和所述BOX层的上部的氮化区域上形成栅介电层; 以及在所述栅极介电层上形成一个或多个栅电极材料; 其中BOX层的上部的氮化区域的存在防止了作为热处理的结果，氧吸附到栅介质层中。

公开(公告)号：US20110269276A1

公开(公告)日：2011-11-03

申请号：US12770792

申请日：2010-04-30

申请人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

发明人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

IPC分类号： H01L21/8238 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。

公开(公告)号：US08643115B2

公开(公告)日：2014-02-04

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US08354313B2

公开(公告)日：2013-01-15

申请号：US12770792

申请日：2010-04-30

申请人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

发明人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

IPC分类号： H01L21/8236 ,  H01L21/8234 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。

公开(公告)号：US20120181616A1

公开(公告)日：2012-07-19

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化的pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US09040399B2

公开(公告)日：2015-05-26

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L21/425 ,  H01L29/66

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US08659091B2

公开(公告)日：2014-02-25

申请号：US13611068

申请日：2012-09-12

申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

摘要翻译： 公开了多晶体管器件及其制造方法。 根据一种方法，形成设置在翅片的多个表面上的翅片和栅极结构。 此外，除去翅片的延伸部的至少一部分以形成位于栅极结构下方的凹陷部分，在鳍的沟道区域下方，并且包括至少一个成角度的凹陷。 此外，端子延伸在通道区域下方并且沿着沟道区域的表面的至少一个成角度的凹陷中生长，使得端子延伸部在沟道区域上提供应力以增强沟道区域中的载流子迁移率。

公开(公告)号：US20130328135A1

公开(公告)日：2013-12-12

申请号：US13494312

申请日：2012-06-12

申请人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

发明人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/66628

摘要： A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.

摘要翻译： 用于晶体管器件的栅极堆叠结构包括形成在衬底上的栅极电介质层; 形成在所述栅极介电层上的第一硅栅极层; 在第一硅栅极层上形成的掺杂剂富含单层; 以及形成在所述富掺杂剂单层上的第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。