公开(公告)号：US08283217B2

公开(公告)日：2012-10-09

申请号：US12717439

申请日：2010-03-04

申请人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

发明人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/762 ,  H01L27/12

摘要： A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing.

摘要翻译： 形成鳍状场效应晶体管（finFET）器件的方法包括在掩埋氧化物（BOX）层上形成多个半导体鳍片; 进行氮注入，以在与多个半导体翅片之间的区域对应的BOX层的上部形成氮化区域; 在所述半导体散热片和所述BOX层的上部的氮化区域上形成栅介电层; 以及在所述栅极介电层上形成一个或多个栅电极材料; 其中BOX层的上部的氮化区域的存在防止了作为热处理的结果，氧吸附到栅介质层中。

公开(公告)号：US20110215405A1

公开(公告)日：2011-09-08

申请号：US12717439

申请日：2010-03-04

申请人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

发明人： Dechao Guo ,  Unoh Kwon ,  Chun-Chen Yeh ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/762 ,  H01L27/12

摘要： A method of forming fin field effect transistor (finFET) devices includes forming a plurality of semiconductor fins over a buried oxide (BOX) layer; performing a nitrogen implant so as to formed nitrided regions in a upper portion of the BOX layer corresponding to regions between the plurality of semiconductor fins; forming a gate dielectric layer over the semiconductor fins and the nitrided regions of the upper portion of the BOX layer; and forming one or more gate electrode materials over the gate dielectric layer; wherein the presence of the nitrided regions of upper portion of the BOX layer prevents oxygen absorption into the gate dielectric layer as a result of thermal processing.

摘要翻译： 形成鳍状场效应晶体管（finFET）器件的方法包括在掩埋氧化物（BOX）层上形成多个半导体鳍片; 进行氮注入，以在与多个半导体翅片之间的区域对应的BOX层的上部形成氮化区域; 在所述半导体散热片和所述BOX层的上部的氮化区域上形成栅介电层; 以及在所述栅极介电层上形成一个或多个栅电极材料; 其中BOX层的上部的氮化区域的存在防止了作为热处理的结果，氧吸附到栅介质层中。

公开(公告)号：US20110269276A1

公开(公告)日：2011-11-03

申请号：US12770792

申请日：2010-04-30

申请人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

发明人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

IPC分类号： H01L21/8238 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。

公开(公告)号：US08643115B2

公开(公告)日：2014-02-04

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US08354313B2

公开(公告)日：2013-01-15

申请号：US12770792

申请日：2010-04-30

申请人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

发明人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

IPC分类号： H01L21/8236 ,  H01L21/8234 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。

公开(公告)号：US20120181616A1

公开(公告)日：2012-07-19

申请号：US13006642

申请日：2011-01-14

申请人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.

摘要翻译： 提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。 等离子体氮化的nFET阈值电压调节的高k栅介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化的pFET阈值电压调节的高k栅介质层部分包括多达15个 原子％N2和位于其中的pFET阈值电压调节物质。

公开(公告)号：US08941177B2

公开(公告)日：2015-01-27

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L29/36 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

公开(公告)号：US08716813B2

公开(公告)日：2014-05-06

申请号：US13556333

申请日：2012-07-24

申请人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/02164 ,  H01L21/02697 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

摘要翻译： 场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层， 与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

公开(公告)号：US08629014B2

公开(公告)日：2014-01-14

申请号：US12885592

申请日：2010-09-20

申请人： Unoh Kwon ,  Michael P. Chudzik ,  Ravikumar Ramachandran

发明人： Unoh Kwon ,  Michael P. Chudzik ,  Ravikumar Ramachandran

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L27/0922 ,  H01L21/823842

摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.

摘要翻译： 在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。 阻挡金属层可以直接沉积在栅极介电层上。 图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。 第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。 或者，第一类功函数层可以直接沉积在栅介电层上。 图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。 第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。 导电材料填充和平坦化形成双重功能替代栅极结构。