公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US09059006B2

公开(公告)日：2015-06-16

申请号：US13523120

申请日：2012-06-14

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

IPC分类号： G01R27/08 ,  H01L23/52 ,  H01L29/10 ,  H01L27/06 ,  H01L23/525 ,  H01L27/112 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US08895371B2

公开(公告)日：2014-11-25

申请号：US13605238

申请日：2012-09-06

申请人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

发明人： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC分类号： H01L21/335 ,  H01L51/05 ,  H01L29/775 ,  H01L29/66 ,  H01L51/00 ,  H01L29/12 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/78

CPC分类号： H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

摘要翻译： 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

公开(公告)号：US08605499B2

公开(公告)日：2013-12-10

申请号：US13092247

申请日：2011-04-22

申请人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

发明人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

IPC分类号： G11C11/50

CPC分类号： H03H9/2457 ,  G11C11/404 ,  G11C23/00 ,  H03H2009/02314

摘要： Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.

摘要翻译： 用栅电极操作纳米级悬臂梁的系统和方法。 示例性系统包括耦合到栅电极的驱动电路，其中来自电路的驱动信号可以使光束在光束的共振频率处或其附近振荡。 驱动信号包括AC分量，并且还可以包括DC分量。 替代示例系统包括纳米级悬臂梁，其中光束振荡以接触多个漏极区域。

公开(公告)号：US20120280322A1

公开(公告)日：2012-11-08

申请号：US13554305

申请日：2012-07-20

申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

摘要： A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w).

摘要翻译： 场效应晶体管器件包括设置在基板上的栅极堆叠，设置在栅极堆叠的第一远端上的第一接触部分，设置在栅极堆叠的第二远端上的第二接触部分，第一接触部分设置距离 （d）从所述第二接触部分和具有设置在所述器件的源极区域中的宽度（w）的第三接触部分，所述距离（d）大于所述宽度（w）。

公开(公告)号：US08288217B2

公开(公告)日：2012-10-16

申请号：US12945026

申请日：2010-11-12

申请人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

摘要翻译： 场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得 沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

公开(公告)号：US08268689B2

公开(公告)日：2012-09-18

申请号：US12860979

申请日：2010-08-23

申请人： Dechao Guo ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L27/088

CPC分类号： H01L29/78696 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

摘要： A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.

摘要翻译： 一种用于制造场效应晶体管器件的方法包括形成第一导电沟道和第二导电沟道，在第一导电沟道上形成第一栅极叠层以部分地限定第一器件，在第二导电沟道上形成第二栅极堆叠以部分地限定 第二装置，注入离子以形成连接到第一导电沟道和第二导电沟道的源极区域和漏极区域，在第二器件上形成掩模层，源极区域的一部分和漏极区域的一部分，执行 第一退火处理，其可操作以改变第一器件的阈值电压，去除掩模层的一部分以暴露第二器件，以及执行可操作以改变第一器件的阈值电压的第二退火处理和第二器件的阈值电压 第二设备

公开(公告)号：US08237457B2

公开(公告)日：2012-08-07

申请号：US12503116

申请日：2009-07-15

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

IPC分类号： G01R27/08 ,  H01L23/52 ,  H01L29/10

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US20110042786A1

公开(公告)日：2011-02-24

申请号：US12543544

申请日：2009-08-19

申请人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

发明人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L28/24

摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.

摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。

公开(公告)号：US08519454B2

公开(公告)日：2013-08-27

申请号：US13075443

申请日：2011-03-30

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/76 ,  H01L21/338 ,  H01L21/84

CPC分类号： H01L29/4966 ,  H01L29/66545 ,  H01L29/7843

摘要： Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

摘要翻译： 本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。 该方法包括在半导体衬底上形成虚拟栅极。 虚拟门包括在第一材料和第二材料之间形成金属层。 该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。 该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。 该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。 该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。