公开(公告)号：US5920515A

公开(公告)日：1999-07-06

申请号：US938062

申请日：1997-09-26

申请人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

发明人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C29/844

摘要： A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.

摘要翻译： 具有内置自修复（BISR）的半导体存储器阵列包括与故障行地址存储相关联的冗余电路以驱动冗余行字线，从而避免替代地址的供应和正常解码。 NOT比较器逻辑将由BISR电路生成和存储的故障行地址与提供给存储器阵列的行地址进行比较。 与NOT比较并行配置的TRUE比较器同时将缺陷行地址信号与提供的行地址进行比较。 由于在没有设置和保持时间约束的情况下，在动态逻辑中不快速执行比较，所以对正常（非冗余）行解码路径的定时影响是可以忽略的，并且由于真正的比较虽然潜在地比NOT比较慢，但是它自身识别冗余行地址 因此不需要对所选字线解码采用N位地址，冗余行寻址是快速的并且不会不利地降低自修复的半导体存储器阵列的性能。 通过在预解码电路级提供冗余处理，而不是在初始地址替换阶段，改进了根据本发明的BISR存储器阵列的访问时间。

公开(公告)号：US5841712A

公开(公告)日：1998-11-24

申请号：US938590

申请日：1997-09-26

申请人： Dennis L. Wendell ,  Benjamin S. Wong

发明人： Dennis L. Wendell ,  Benjamin S. Wong

IPC分类号： G06F12/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/14 ,  G11C11/408 ,  G11C11/412 ,  G11C11/418 ,  G11C29/00 ,  G11C29/02 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  H03K3/356 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C11/4087 ,  G11C11/412 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/14 ,  H03K3/356156 ,  H03K5/13 ,  H03L7/08 ,  G11C11/401 ,  G11C11/41 ,  G11C16/04 ,  G11C17/14 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/0995

摘要： A redundancy circuit and method allows replacement of failed memory cells in a semiconductor memory array. Redundancy true and redundancy not comparator circuits are provided in dynamic logic to selectively enable and disable respective redundant row predecode and normal row predecode circuits. In one embodiment, redundancy circuits are row redundancy circuits. As compared with single static row redundancy comparator circuits which are limited by setup time constraints and which degrade access time irrespective of redundant row utilization, a dual dynamic comparator design reduces access time penalties when redundancy is enabled and eliminates access time penalties when redundancy is not required in a particular semiconductor memory array.

摘要翻译： 冗余电路和方法允许替换半导体存储器阵列中的故障存储器单元。 在动态逻辑中提供冗余真实和冗余不是比较器电路，以选择性地启用和禁用相应的冗余行预解码和正常行预解码电路。 在一个实施例中，冗余电路是行冗余电路。 与单个静态行冗余比较器电路相比，其受到建立时间约束的限制，并且与冗余行利用率无关地降低了访问时间，双重动态比较器设计减少了冗余启用时的访问时间损失，并且在不需要冗余时消除了访问时间损失 在特定的半导体存储器阵列中。

公开(公告)号：US06645610B1

公开(公告)日：2003-11-11

申请号：US09583605

申请日：2000-05-31

申请人： Carl Andrew Reis ,  Benjamin S. Wong

发明人： Carl Andrew Reis ,  Benjamin S. Wong

IPC分类号： B32B302

CPC分类号： B29C70/24 ,  B29C37/0082 ,  B29C70/54 ,  B32B3/06 ,  Y10T428/23943 ,  Y10T428/23957 ,  Y10T428/23964 ,  Y10T428/24994

摘要： A cured composite material formed in accordance with the method of the present invention. The method initially providing for providing a peel-ply sheet which defines opposed planar faces. A multitude of elongate bond fibers are embedded into the peel-ply sheet in a manner wherein a majority of the bond fibers do not extend in co-planar relation to the planar faces of the peel-ply sheet. A resin composite material is provided. The peel-ply sheet is applied to the resin composite material such that the bond fibers are partially embedded therein. The resin composite material is cured. The peel-ply sheet is removed from the cured resin composite material such that the bond fibers remain implanted therein.

摘要翻译： 根据本发明的方法形成的固化的复合材料。 该方法最初提供了提供限定相对的平面的剥离片。 许多细长的粘合纤维以其中绝大多数粘合纤维不与剥离片的平面相互平行的关系延伸的方式嵌入剥离片中。 提供树脂复合材料。 将剥离片施加到树脂复合材料上，使得粘合纤维部分地嵌入其中。 树脂复合材料固化。 从固化树脂复合材料中除去剥离片，使得粘合纤维保持植入其中。

公开(公告)号：US07327597B1

公开(公告)日：2008-02-05

申请号：US10412566

申请日：2003-04-11

申请人： Benjamin S. Wong

发明人： Benjamin S. Wong

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C5/063 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12

摘要： An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit line pairs, and a second set or group or stage of SRAM banks are coupled to a second data bus formed using other bit line pairs. The number of banks coupled to each bit line pair is determined by the SRAM's operating frequency and size. Each data bus is coupled to a sense amplifier. The output from the sense amplifier is then coupled to the bit line pair of a group of SRAM banks. This adjacent group has staging logic coupled to each SRAM bank to store the output of the SRAM bank until the contents from the first group is placed on the bit line of the adjacent stage of SRAM banks. The output from either the first stage or from one of the SRAM banks in the adjacent stage's SRAM banks, which had been stored in the adjacent stage's staging logic, is driven to the sense amplifier coupled to the adjacent stage. Successive stages of SRAM banks can be coupled together until an arbitrary number of stages of SRAM banks have been coupled together.

摘要翻译： 描述了用于半导体静态随机存取存储器（SRAM）的架构。 在一个示例中，第一集合或一组或多个SRAM组耦合到使用位线对形成的第一数据总线，并且第二组或一组或多个SRAM组耦合到使用其它位线形成的第二数据总线 对。 耦合到每个位线对的存储体的数量由SRAM的工作频率和大小决定。 每个数据总线耦合到读出放大器。 然后，来自读出放大器的输出被耦合到一组SRAM存储体的位线对。 该相邻组具有耦合到每个SRAM组的分级逻辑，以存储SRAM组的输出，直到来自第一组的内容被放置在相邻级的SRAM组的位线上。 已经存储在相邻级的分级逻辑中的来自相邻级的SRAM存储体中的来自第一级或来自一个SRAM存储体的输出被驱动到耦合到相邻级的读出放大器。 SRAM库的连续级可以耦合在一起，直到SRAM组的任意数量级耦合在一起。

公开(公告)号：US6124000A

公开(公告)日：2000-09-26

申请号：US248172

申请日：1999-02-09

申请人： Jerry Wynn Brimer ,  Ernie Robert Silva ,  William K. Oehlert, deceased ,  James A. Kirk ,  Benjamin S. Wong

发明人： Jerry Wynn Brimer ,  Ernie Robert Silva ,  William K. Oehlert, deceased ,  James A. Kirk ,  Benjamin S. Wong

IPC分类号： B05D1/06 ,  B05D7/14 ,  B05D1/12 ,  B05D1/04

CPC分类号： B05D7/14 ,  B05D1/06 ,  Y10T428/24994 ,  Y10T428/24995 ,  Y10T428/249951 ,  Y10T428/249952 ,  Y10T428/254 ,  Y10T428/31678 ,  Y10T428/31681

摘要： A method of rendering a surface of a metal substrate substantially acid impervious. The method includes first placing the surface in a field of treatment, then depositing a mixture of a high-temperature resistant polymer particulate such as polyamide particulate and a curable powder adhesive on the surface, and finally subjecting the surface-coated metal substrate to a curing treatment sufficient to cure the powder adhesive and thereby adhere the polymer particulate as a film on the surface. A steel substrate coated in accord with the present methodology is particularly useful as a curing fixture upon which resin-impregnated fiber of polymer composite material is placed to thereby give molded parts made therefrom a desired shape. Production of a part is accomplished by vacuum bagging the composite material to the steel fixture and curing the so-produced part in place on the fixture in an autoclave at an elevated temperature. In this manner the acid impervious curing fixture allows production of composite parts without the danger of leaching iron from the fixture to thus assure full-utility part fabrication.

摘要翻译： 使金属基材的表面呈现基本上不透水的方法。 该方法包括首先将表面放置在处理领域中，然后将耐高温聚合物颗粒如聚酰胺颗粒和可固化粉末粘合剂的混合物沉积在表面上，最后对表面涂覆的金属基材进行固化 足以固化粉末粘合剂，从而将聚合物颗粒作为膜粘附在表面上。 根据本方法涂覆的钢基材作为固化固化剂是特别有用的，聚合物复合材料的树脂浸渍纤维被放置在其上，从而由其制成所需形状的模塑部件。 通过将复合材料真空包装到钢固定装置并在高压釜中在高温下将所制造的部件固化在固定装置上的位置上来实现零件的制造。 以这种方式，不透水的固化固化装置允许生产复合材料部件，而不会从固定装置中浸出铁，从而确保完全实用的零件制造。

公开(公告)号：US07630230B2

公开(公告)日：2009-12-08

申请号：US11948812

申请日：2007-11-30

申请人： Benjamin S. Wong

发明人： Benjamin S. Wong

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C5/063 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12

摘要： An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit line pairs, and a second set or group or stage of SRAM banks are coupled to a second data bus formed using other bit line pairs. The number of banks coupled to each bit line pair is determined by the SRAM's operating frequency and size. Each data bus is coupled to a sense amplifier. The output from the sense amplifier is then coupled to the bit line pair of a group of SRAM banks. This adjacent group has staging logic coupled to each SRAM bank to store the output of the SRAM bank until the contents from the first group is placed on the bit line of the adjacent stage of SRAM banks. The output from either the first stage or from one of the SRAM banks in the adjacent stage's SRAM banks, which had been stored in the adjacent stage's staging logic, is driven to the sense amplifier coupled to the adjacent stage. Successive stages of SRAM banks can be coupled together until an arbitrary number of stages of SRAM banks have been coupled together.

摘要翻译： 描述了用于半导体静态随机存取存储器（SRAM）的架构。 在一个示例中，第一集合或一组或多个SRAM组耦合到使用位线对形成的第一数据总线，并且第二组或一组或多个SRAM组耦合到使用其它位线形成的第二数据总线 对。 耦合到每个位线对的存储体的数量由SRAM的工作频率和大小决定。 每个数据总线耦合到读出放大器。 然后，来自读出放大器的输出被耦合到一组SRAM存储体的位线对。 该相邻组具有耦合到每个SRAM组的分级逻辑，以存储SRAM组的输出，直到来自第一组的内容被放置在相邻级的SRAM组的位线上。 已经存储在相邻级的分级逻辑中的来自相邻级的SRAM存储体中的来自第一级或来自一个SRAM存储体的输出被驱动到耦合到相邻级的读出放大器。 SRAM库的连续级可以耦合在一起，直到SRAM组的任意数量级耦合在一起。

公开(公告)号：US20080144361A1

公开(公告)日：2008-06-19

申请号：US11948812

申请日：2007-11-30

申请人： Benjamin S. Wong

发明人： Benjamin S. Wong

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C11/413 ,  G11C5/063 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12

摘要： An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit line pairs, and a second set or group or stage of SRAM banks are coupled to a second data bus formed using other bit line pairs. The number of banks coupled to each bit line pair is determined by the SRAM's operating frequency and size. Each data bus is coupled to a sense amplifier. The output from the sense amplifier is then coupled to the bit line pair of a group of SRAM banks. This adjacent group has staging logic coupled to each SRAM bank to store the output of the SRAM bank until the contents from the first group is placed on the bit line of the adjacent stage of SRAM banks. The output from either the first stage or from one of the SRAM banks in the adjacent stage's SRAM banks, which had been stored in the adjacent stage's staging logic, is driven to the sense amplifier coupled to the adjacent stage. Successive stages of SRAM banks can be coupled together until an arbitrary number of stages of SRAM banks have been coupled together.

摘要翻译： 描述了用于半导体静态随机存取存储器（SRAM）的架构。 在一个示例中，第一集合或一组或多个SRAM组耦合到使用位线对形成的第一数据总线，并且第二组或一组或多个SRAM组耦合到使用其它位线形成的第二数据总线 对。 耦合到每个位线对的存储体的数量由SRAM的工作频率和大小决定。 每个数据总线耦合到读出放大器。 然后，来自读出放大器的输出被耦合到一组SRAM存储体的位线对。 该相邻组具有耦合到每个SRAM组的分级逻辑，以存储SRAM组的输出，直到来自第一组的内容被放置在相邻级的SRAM组的位线上。 已经存储在相邻级的分级逻辑中的来自相邻级的SRAM存储体中的来自第一级或来自一个SRAM存储体的输出被驱动到耦合到相邻级的读出放大器。 SRAM库的连续级可以耦合在一起，直到SRAM组的任意数量级耦合在一起。

公开(公告)号：US06805947B1

公开(公告)日：2004-10-19

申请号：US09632017

申请日：2000-08-02

申请人： Jerry Wynn Brimer ,  Ernie Robert Silva ,  William K. Oehlert ,  James A. Kirk ,  Benjamin S. Wong

发明人： Jerry Wynn Brimer ,  Ernie Robert Silva ,  William K. Oehlert ,  James A. Kirk ,  Benjamin S. Wong

IPC分类号： B32B1508

CPC分类号： B05D7/14 ,  B05D1/06 ,  Y10T428/24994 ,  Y10T428/24995 ,  Y10T428/249951 ,  Y10T428/249952 ,  Y10T428/254 ,  Y10T428/31678 ,  Y10T428/31681

摘要： A method of rendering a surface of a metal substrate substantially acid impervious. The method includes first placing the surface in a field of treatment, then depositing a mixture of a high-temperature resistant polymer particulate such as polyamide particulate and a curable powder adhesive on the surface, and finally subjecting the surface-coated metal substrate to a curing treatment sufficient to cure the powder adhesive and thereby adhere the polymer particulate as a film on the surface. A steel substrate coated in accord with the present methodology is particularly useful as a curing fixture upon which resin-impregnated fiber of polymer composite material is placed to thereby give molded parts made therefrom a desired shape. Production of a part is accomplished by vacuum bagging the composite material to the steel fixture and curing the so-produced part in place on the fixture in an autoclave at an elevated temperature. In this manner the acid impervious curing fixture allows production of composite parts without the danger of leaching iron from the fixture to thus assure full-utility part fabrication.

摘要翻译： 使金属基材的表面呈现基本上不透水的方法。 该方法包括首先将表面放置在处理领域中，然后将耐高温聚合物颗粒如聚酰胺颗粒和可固化粉末粘合剂的混合物沉积在表面上，最后对表面涂覆的金属基材进行固化 足以固化粉末粘合剂，从而将聚合物颗粒作为膜粘附在表面上。 根据本方法涂覆的钢基材作为固化固化剂是特别有用的，聚合物复合材料的树脂浸渍纤维被放置在其上，从而由其制成所需形状的模塑部件。 通过将复合材料真空包装到钢固定装置并在高压釜中在高温下将所制造的部件固化在固定装置上的位置上来实现零件的制造。 以这种方式，不透水的固化固化装置允许生产复合材料部件，而不会从固定装置中浸出铁，从而确保完全实用的零件制造。

公开(公告)号：US5879492A

公开(公告)日：1999-03-09

申请号：US62544

申请日：1998-04-17

申请人： Carl Andrew Reis ,  Benjamin S. Wong

发明人： Carl Andrew Reis ,  Benjamin S. Wong

IPC分类号： B29C70/24 ,  B32B7/04 ,  B32B5/00

CPC分类号： B32B7/04 ,  B29C70/24

摘要： In accordance with the present invention, there is provided a method of increasing the surface bond strength characteristics of a resin composite material. The method begins with providing a peel-ply sheet which defines opposed planar faces. A multitude of elongate bond fibers are embedded into the peel-ply sheet in a manner in which a majority of the bond fibers do not extend in co-planar relation to the planar faces of the peel-ply sheet. A resin composite material is provided. The peel-ply sheet is applied to the resin composite material such that the bond fibers are partially embedded therein. The resin composite material is cured. The peel-ply sheet is removed from the cured resin composite material such that the bond fibers remain implanted therein.

摘要翻译： 根据本发明，提供了增加树脂复合材料的表面粘结强度特性的方法。 该方法开始于提供限定相对的平面的剥离片。 许多细长粘合纤维以其中大部分粘合纤维不以剥离层的平面相互共面的方式延伸的方式嵌入剥离片中。 提供树脂复合材料。 将剥离片施加到树脂复合材料上，使得粘合纤维部分地嵌入其中。 树脂复合材料固化。 从固化树脂复合材料中除去剥离片，使得粘合纤维保持植入其中。