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    Differential current switch logic gate
    1.
    发明授权
    Differential current switch logic gate 失效
    差分电流开关逻辑门

    公开(公告)号：US6014041A

    公开(公告)日：2000-01-11

    申请号：US937832

    申请日：1997-09-26

    申请人： Dinesh Somasekhar ,  Kaushik Roy ,  Junji Sugisawa

    发明人： Dinesh Somasekhar ,  Kaushik Roy ,  Junji Sugisawa

    IPC分类号： H03K3/356 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H03K3/356165 ,  H03K3/356113

    摘要： A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

    摘要翻译： 提供了具有包括多个输入端子和一对互补输出节点的评估树的差分电流开关逻辑（DCSL）系统。 DCSL系统还具有输出网络，其在预充电阶段期间以预定电平建立一对状态输出，并且在评估阶段期间响应于评估树输出节点建立互补电平的状态输出。 第一和第二NMOS晶体管串联连接在DCVS输出状态网络和评估树输出节点之间，其门耦合到状态输出，以将评估树的输出与评估树隔离。

    Variation-tolerant self-repairing displays
    2.
    发明授权
    Variation-tolerant self-repairing displays 有权
    耐变性自修复显示

    公开(公告)号：US08994396B2

    公开(公告)日：2015-03-31

    申请号：US13349722

    申请日：2012-01-13

    申请人： Chih-Hsiang Ho ,  Chao Lu ,  Debabrata Mohapatra ,  Kaushik Roy

    发明人： Chih-Hsiang Ho ,  Chao Lu ,  Debabrata Mohapatra ,  Kaushik Roy

    IPC分类号： G01R31/26 ,  G09G3/32 ,  G09G3/36

    CPC分类号： G09G3/3233 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2330/08 ,  G09G2330/10 ,  G09G2330/12

    摘要： Illustrative embodiments of systems and methods for variation-tolerant, self-repairing displays are disclosed. In one illustrative embodiment, a display panel may include one or more defective pixels and a compensation circuit may be configured to extend a charging time of each of the one or more defective pixels. In another illustrative embodiment, a method may include detecting one or more defective pixels in a pixel array and extending a charging time of each of the one or more defective pixels.

    摘要翻译： 公开了用于变形容忍的自修复显示器的系统和方法的说明性实施例。 在一个说明性实施例中，显示面板可以包括一个或多个缺陷像素，并且补偿电路可以被配置为延长一个或多个缺陷像素中的每一个的充电时间。 在另一个说明性实施例中，一种方法可以包括检测像素阵列中的一个或多个缺陷像素并且延长一个或多个缺陷像素中的每一个的充电时间。

    Variation-Tolerant Self-Repairing Displays
    5.
    发明申请
    Variation-Tolerant Self-Repairing Displays 有权
    耐变形自修复显示器

    公开(公告)号：US20120182518A1

    公开(公告)日：2012-07-19

    申请号：US13349722

    申请日：2012-01-13

    申请人： Chih-Hsiang Ho ,  Chao Lu ,  Debabrata Mohapatra ,  Kaushik Roy

    发明人： Chih-Hsiang Ho ,  Chao Lu ,  Debabrata Mohapatra ,  Kaushik Roy

    IPC分类号： H01J9/50 ,  G02F1/13

    CPC分类号： G09G3/3233 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2330/08 ,  G09G2330/10 ,  G09G2330/12

    摘要： Illustrative embodiments of systems and methods for variation-tolerant, self-repairing displays are disclosed. In one illustrative embodiment, a display panel may include one or more defective pixels and a compensation circuit may be configured to extend a charging time of each of the one or more defective pixels. In another illustrative embodiment, a method may include detecting one or more defective pixels in a pixel array and extending a charging time of each of the one or more defective pixels.

    摘要翻译： 公开了用于变形容忍的自修复显示器的系统和方法的说明性实施例。 在一个说明性实施例中，显示面板可以包括一个或多个缺陷像素，并且补偿电路可以被配置为延长一个或多个缺陷像素中的每一个的充电时间。 在另一个说明性实施例中，一种方法可以包括检测像素阵列中的一个或多个缺陷像素并且延长一个或多个缺陷像素中的每一个的充电时间。

    Static random access memory cell and devices using same
    6.
    发明授权
    Static random access memory cell and devices using same 有权
    静态随机存取存储单元和使用相同的器件

    公开(公告)号：US07952912B2

    公开(公告)日：2011-05-31

    申请号：US12134352

    申请日：2008-06-06

    申请人： Jaydeep P. Kulkarni ,  Kaushik Roy

    发明人： Jaydeep P. Kulkarni ,  Kaushik Roy

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled to a right inverter of the cross-coupled inverters via a right word-line transistor and a right write-line transistor. The word-line may be coupled to the gates of the left and right word-line transistors and the write-line may be coupled to the gates of the left and right write-line transistors. A memory device may include a controller, an array of such bit-cells and a differential sensing buffers. Further, a computing device may include a processor and a memory device having the above bit-cells.

    摘要翻译： 位单元可以包括一对交叉耦合的反相器，左位线，右位线，字线和写入线。 左位线可以经由左字线晶体管和左写线晶体管耦合到交叉耦合的反相器的左反相器。 右位线可以经由右字线晶体管和右写线晶体管耦合到交叉耦合的反相器的右反相器。 字线可以耦合到左和右字线晶体管的栅极，并且写线可以耦合到左和右写入线晶体管的栅极。 存储器件可以包括控制器，这样的位单元的阵列和差分感测缓冲器。 此外，计算设备可以包括具有上述位单元的处理器和存储器件。

    Static random access memory cell and devices using same
    7.
    发明申请
    Static random access memory cell and devices using same 有权
    静态随机存取存储单元和使用相同的器件

    公开(公告)号：US20090303775A1

    公开(公告)日：2009-12-10

    申请号：US12134352

    申请日：2008-06-06

    申请人： Jaydeep P. Kulkarni ,  Kaushik Roy

    发明人： Jaydeep P. Kulkarni ,  Kaushik Roy

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled to a right inverter of the cross-coupled inverters via a right word-line transistor and a right write-line transistor. The word-line may be coupled to the gates of the left and right word-line transistors and the write-line may be coupled to the gates of the left and right write-line transistors. A memory device may include a controller, an array of such bit-cells and a differential sensing buffers. Further, a computing device may include a processor and a memory device having the above bit-cells.

    摘要翻译： 位单元可以包括一对交叉耦合的反相器，左位线，右位线，字线和写入线。 左位线可以经由左字线晶体管和左写线晶体管耦合到交叉耦合的反相器的左反相器。 右位线可以经由右字线晶体管和右写线晶体管耦合到交叉耦合的反相器的右反相器。 字线可以耦合到左和右字线晶体管的栅极，并且写线可以耦合到左和右写入线晶体管的栅极。 存储器件可以包括控制器，这样的位单元的阵列和差分感测缓冲器。 此外，计算设备可以包括具有上述位单元的处理器和存储器件。

    Low power scan design and delay fault testing technique using first level supply gating
    8.
    发明授权
    Low power scan design and delay fault testing technique using first level supply gating 失效
    低功耗扫描设计和延时故障测试技术采用一级电源门控

    公开(公告)号：US07319343B2

    公开(公告)日：2008-01-15

    申请号：US11099386

    申请日：2005-04-05

    申请人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    发明人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    IPC分类号： H03K19/173 ,  G01R31/28

    CPC分类号： G01R31/31858

    摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

    摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。

    Apparatus and methods for determining memory device faults
    9.
    发明申请
    Apparatus and methods for determining memory device faults 有权
    用于确定存储器件故障的装置和方法

    公开(公告)号：US20070242538A1

    公开(公告)日：2007-10-18

    申请号：US11404667

    申请日：2006-04-14

    申请人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    发明人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50016

    摘要： A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

    摘要翻译： 用于确定存储器件中的故障的测试电路。 测试电路包括：读取电路，被配置为在第一时刻和第二时刻读取存储器件中的存储单元内容。 测试电路包括比较第一和第二时刻的内容的比较器。 如果内容不同，则比较器指示发生故障。 测试方法也用于确定存储器单元中是否发生故障。

    Semiconductor device for low power operation
    10.
    发明申请
    Semiconductor device for low power operation 审中-公开
    用于低功率运行的半导体器件

    公开(公告)号：US20060081936A1

    公开(公告)日：2006-04-20

    申请号：US11229226

    申请日：2005-09-16

    申请人： Jae-Joon Kim ,  Kaushik Roy

    发明人： Jae-Joon Kim ,  Kaushik Roy

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7831 ,  H01L27/088 ,  H01L29/78648

    摘要： A semiconductor device for low power operation includes a channel region having a channel length greater than a standard minimum channel length. The voltage supply of the device is less than the threshold voltage of the device. A gate terminal of the device may have a raised height relative to a source and drain region of the device. In one embodiment, the semiconductor device is a double gate metal-oxide field effect transistor.

    摘要翻译： 用于低功率操作的半导体器件包括具有大于标准最小沟道长度的沟道长度的沟道区。 器件的电源电压小于器件的阈值电压。 器件的栅极端子可以相对于器件的源极和漏极区域具有升高的高度。 在一个实施例中，半导体器件是双栅极金属氧化物场效应晶体管。