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    Enhanced T-gate structure for modulation doped field effect transistors
    2.
    发明授权
    Enhanced T-gate structure for modulation doped field effect transistors 有权
    用于调制掺杂场效应晶体管的增强型T栅极结构

    公开(公告)号：US06972440B2

    公开(公告)日：2005-12-06

    申请号：US10750697

    申请日：2004-01-02

    申请人： Dinkar Singh ,  Katherine Lynn Saenger ,  Vishnubhai V. Patel ,  Alfred Grill ,  Steven John Koester

    发明人： Dinkar Singh ,  Katherine Lynn Saenger ,  Vishnubhai V. Patel ,  Alfred Grill ,  Steven John Koester

    IPC分类号： H01L21/285 ,  H01L29/423 ,  H01L31/0328

    CPC分类号： H01L21/28587 ,  H01L29/42316

    摘要： A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

    摘要翻译： 公开了用于调制掺杂场效应晶体管（MODFET）的增强型T栅极的结构和方法。 增强型T型栅极具有夹持T型栅极颈部的绝缘体隔离层。 间隔层比T形杆部分突出部薄。 绝缘层提供机械支撑并保护T型门的易损颈部在后续装置处理过程中不会发生化学侵蚀，从而使T型门结构具有高度的可伸缩性并提高产量。 使用薄的共形低介电常数绝缘层确保低的寄生栅极电容，并且当源极到栅极间隔减小到更小的尺寸时，可以降低栅极和源极冶金的短路的风险。

    Method and materials for through-mask electroplating and selective base removal
    7.
    发明授权
    Method and materials for through-mask electroplating and selective base removal 失效
    用于通孔电镀和选择性基底去除的方法和材料

    公开(公告)号：US06391773B2

    公开(公告)日：2002-05-21

    申请号：US09733188

    申请日：2000-12-09

    申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    IPC分类号： H01L2144

    CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

    摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

    摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

    Structure and fabrication method for non-planar memory elements
    8.
    发明授权
    Structure and fabrication method for non-planar memory elements 失效
    非平面记忆元件的结构和制造方法

    公开(公告)号：US06242321B1

    公开(公告)日：2001-06-05

    申请号：US09303595

    申请日：1999-05-03

    申请人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

    发明人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

    IPC分类号： H01L2176

    CPC分类号： H01L27/10852 ,  H01L28/55

    摘要： Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

    摘要翻译： 用于存储器单元应用的结构，包括用于DRAM的电容器和来自FRAM的铁电存储器单元，其制造方法包括沉积铁电体或高ε电介质材料以完全填充空腔，其几何宽度是电学厚度的唯一决定因素 最终装置中铁电或高ε电介质层的有效部分。 在优选实施例中，沉积电介质的空腔由在电介质沉积之前的通过掩模镀层步骤中沉积和图案化的板和堆叠电极之间的间隙限定。

    Method and materials for through-mask electroplating and selective base removal
    9.
    发明授权
    Method and materials for through-mask electroplating and selective base removal 失效
    用于通孔电镀和选择性基底去除的方法和材料

    公开(公告)号：US06188120B1

    公开(公告)日：2001-02-13

    申请号：US08805403

    申请日：1997-02-24

    申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    IPC分类号： H01L27108

    CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

    摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

    摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

    Isolated sidewall capacitor
    10.
    发明授权
    Isolated sidewall capacitor 失效
    隔离侧壁电容器

    公开(公告)号：US6027966A

    公开(公告)日：2000-02-22

    申请号：US910179

    申请日：1997-08-13

    申请人： Katherine Lynn Saenger ,  James H. Comfort ,  Alfred Grill ,  David Edward Kotecki

    发明人： Katherine Lynn Saenger ,  James H. Comfort ,  Alfred Grill ,  David Edward Kotecki

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70

    CPC分类号： H01L28/55 ,  H01L27/10852 ,  Y10T29/435

    摘要： A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.

    摘要翻译： 提供一种电容器结构，其中第一导体位于衬底的顶部，第一非导体位于第一导体之上，并且基本上与第一导体对准，第一导体和第一非导体具有形成在其中的第一开口， 形成在第一开口中的导电侧壁间隔物，其中形成有第二开口的非导电侧壁隔离物和形成在第二开口中的第二导体。