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    Systems and methods for distinguishing between memory types
    1.
    发明授权
    Systems and methods for distinguishing between memory types 失效
    用于区分内存类型的系统和方法

    公开(公告)号：US06012122A

    公开(公告)日：2000-01-04

    申请号：US769588

    申请日：1996-12-18

    申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Oh-Seung Kwon

    发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Oh-Seung Kwon

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G06F12/06 ,  G11C7/20 ,  G11C11/4072

    CPC分类号： G11C11/4072 ,  G11C7/20

    摘要： A plurality of memory types are distinguished from one another in memory systems containing a plurality of memory types by applying an input signal to the memory system containing the plurality of memory types and detecting differing outputs from the plurality of memory types during a predetermined time period after the input signal is applied. Extended data output (EDO), dynamic random access memories (DRAM) are thereby distinguished from fast page mode (F/P) DRAM. Similarly, nonvolatile memory such as DRAM interface flash memory (DIFM) are distinguished from conventional DRAMs.

    摘要翻译： 多个存储器类型在包含多种存储器类型的存储器系统中通过将输入信号施加到包含多种存储器类型的存储器系统并且在预定时间段之后的多个存储器类型中检测不同的输出而彼此区分开 输入信号被施加。 扩展数据输出（EDO），动态随机存取存储器（DRAM）从而与快速页模式（F / P）DRAM区分开。 类似地，诸如DRAM接口闪存（DIFM）的非易失性存储器与常规DRAM不同。

    Self-contained reprogramming nonvolatile integrated circuit memory devices and methods
    2.
    发明授权
    Self-contained reprogramming nonvolatile integrated circuit memory devices and methods 失效
    独立的重新编程非易失性集成电路存储器件和方法

    公开(公告)号：US5732018A

    公开(公告)日：1998-03-24

    申请号：US739276

    申请日：1996-10-29

    申请人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

    发明人： Do-Chan Choi ,  Tae-Sung Jung ,  Woung-Moo Lee ,  Ejaz Haq ,  Syed Ali

    IPC分类号： G11C17/00 ,  G11C5/02 ,  G11C7/10 ,  G11C16/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C11/34 ,  G11C7/00

    CPC分类号： G11C5/025 ,  G11C16/28 ,  G11C7/1051

    摘要： Nonvolatile integrated circuit memory devices, such as EEPROMs, use unselected shared latching sense amplifiers to latch data from memory cells which are to be reprogrammed after a page erase, and to resupply the latch data to the memory cells which are to be programmed after erase, to thereby internally reprogram the latched data into erased memory cells after page programming. Transferring circuits and methods are provided for transferring data between shared latching sense amplifiers to permit internal reprogramming. High speed and simplified reprogramming of EEPROMs is thereby provided.

    摘要翻译： 非易失性集成电路存储器件（例如EEPROM）使用未选择的共享锁存读出放大器来锁存来自在擦除之后要重新编程的存储器单元的数据，并且将锁存数据重新供给到擦除后要被编程的存储器单元， 从而在页编程之后将锁存的数据内部重新编程为擦除的存储器单元。 传送电路和方法用于在共享锁存读出放大器之间传输数据，以允许内部重新编程。 从而提供EEPROM的高速和简化重新编程。

    Nonvolatile semiconductor memory which is connectable to a DRAM bus
    3.
    发明授权
    Nonvolatile semiconductor memory which is connectable to a DRAM bus 失效
    可连接到DRAM总线的非易失性半导体存储器

    公开(公告)号：US5737258A

    公开(公告)日：1998-04-07

    申请号：US638100

    申请日：1996-04-26

    申请人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

    发明人： Do-Chan Choi ,  Woung-Moo Lee ,  Tae-Sung Jung ,  Syed Ali ,  Ejaz Haq

    IPC分类号： G11C17/00 ,  G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16

    CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C5/025 ,  G11C5/066

    摘要： An electrically erasable and programmable nonvolatile memory device (EEPROM) such as a flash memory, is pin compatible with a dynamic random access memory device (DRAM), such that flash memory may be connected to a DRAM bus. Preferably, the flash memory is read and write timing-compatible with the DRAM read and write signals and is also preferably block read and block write timing compatible with DRAM block read and block write signals. The flash memory accepts signals to perform sleep and erase functions from signal lines of a DRAM bus which are not used by a DRAM. In order to perform a block erase, which is a characteristic of flash memory, the device preferably accepts an instruction to perform a block erase from signal lines of a DRAM bus which are not used by a DRAM and a block address for the block erase from the most significant bit address lines of the DRAM bus.

    摘要翻译： 诸如闪速存储器的电可擦除和可编程的非易失性存储器件（EEPROM）与动态随机存取存储器件（DRAM）引脚兼容，使得闪速存储器可以连接到DRAM总线。 优选地，闪速存储器是与DRAM读取和写入信号时序兼容的读取和写入，并且还优选地是与DRAM块读取和写入信号兼容的块读取和块写入定时。 闪速存储器接受信号以从未被DRAM使用的DRAM总线的信号线执行睡眠和擦除功能。 为了执行作为闪速存储器的特征的块擦除，设备优选地接受从DRAM不使用的DRAM总线的信号线执行块擦除的指令和用于块擦除的块地址 DRAM总线的最高有效位地址线。

    Nonvolatile memory devices including lockable word line cells
    4.
    发明授权
    Nonvolatile memory devices including lockable word line cells 失效
    包括可锁定字线单元的非易失性存储器件

    公开(公告)号：US5809553A

    公开(公告)日：1998-09-15

    申请号：US770260

    申请日：1996-12-20

    申请人： Do-Chan Choi ,  Jong-Chang Son

    发明人： Do-Chan Choi ,  Jong-Chang Son

    IPC分类号： G11C17/00 ,  G06F21/02 ,  G11C8/20 ,  G11C16/02 ,  G11C16/04 ,  G11C16/22 ,  G06F12/00

    CPC分类号： G11C16/22 ,  G11C8/20

    摘要： Nonvolatile memory devices and methods include an array of nonvolatile memory cells which are arranged in a plurality of rows and a plurality of columns. A plurality of word lines are also included, a respective one of which is connected to the nonvolatile memory cells in a respective one of a plurality of columns. A plurality of lockable cells are also included. A respective one of the lockable cells is connected to a respective one of the plurality of word lines. Each of the lockable cells stores therein a first or a second binary value. The first binary value indicates that nonvolatile memory cells which are connected to the corresponding column of word lines cannot be erased or reprogrammed. The second binary value indicates that nonvolatile memory cells which are connected to the corresponding column of words lines can be erased or programmed.

    摘要翻译： 非易失性存储器件和方法包括排列成多行和多列的非易失性存储单元阵列。 还包括多个字线，其相应的一个字线连接到多个列中的相应一个中的非易失性存储单元。 还包括多个可锁定单元。 可锁定单元中的相应一个连接到多个字线中的相应一个字线。 每个可锁电池在其中存储第一或第二二进制值。 第一个二进制值表示连接到相应列的字线的非易失性存储单元不能被擦除或重新编程。 第二个二进制值表示可以擦除或编程连接到相应列的字线的非易失性存储单元。

    Input protection circuit and method for semiconductor memory device
    5.
    发明授权
    Input protection circuit and method for semiconductor memory device 失效
    半导体存储器件的输入保护电路及方法

    公开(公告)号：US5717354A

    公开(公告)日：1998-02-10

    申请号：US632591

    申请日：1996-04-15

    申请人： Myung-Jae Kim ,  Do-Chan Choi

    发明人： Myung-Jae Kim ,  Do-Chan Choi

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/34 ,  G11C11/413 ,  H03K5/08 ,  H03K19/00

    CPC分类号： H03K5/08 ,  G11C7/1048 ,  G11C7/1078

    摘要： An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.

    摘要翻译： 用于半导体存储器件的输入保护电路检测何时外部输入信号的电平低于对应于预定逻辑电平的参考电压，由此使得能立即校正。 输入保护电路插入到外部电源电压端子和输入缓冲器的输入端子之间，当施加到输入端子的外部输入信号的电平下降时，外部电源电压被传送到输入缓冲器的输入端子 低于预定逻辑电平。 该电路包括内部参考电压发生器，其提供具有与预定逻辑电平相对应的电平的电压，并被设计为补偿已知的器件偏移，使得可以立即校正施加到输入端的外部输入信号。

    Memory module and memory system
    7.
    发明申请
    Memory module and memory system 审中-公开
    内存模块和内存系统

    公开(公告)号：US20070038831A1

    公开(公告)日：2007-02-15

    申请号：US11416332

    申请日：2006-05-02

    申请人： Hong-Kyun Kim ,  Do-Chan Choi

    发明人： Hong-Kyun Kim ,  Do-Chan Choi

    IPC分类号： G06F13/00

    CPC分类号： G11C5/04 ,  G11C7/22 ,  G11C2207/2245

    摘要： A memory module includes a plurality of semiconductor memory devices, a plurality of module tabs and a memory buffer. The plurality of the semiconductor memory devices stores first data, wherein at least one of the plurality of the semiconductor memory devices has a lower latency. The plurality of the module tabs is used to transfer a signal and data to/from an external device. The memory buffer buffers the first data output from the semiconductor memory devices to the module tabs and buffers second data and a signal provided from an external device through the module tabs to the semiconductor memory devices. Therefore, a latency of a memory module may be reduced.

    摘要翻译： 存储器模块包括多个半导体存储器件，多个模块标签和存储器缓冲器。 多个半导体存储器件存储第一数据，其中多个半导体存储器件中的至少一个具有较低的延迟。 多个模块标签用于将信号和数据传送到/从外部设备传送。 存储器缓冲器将从半导体存储器件输出的第一数据缓冲到模块标签上，并将第二数据和从外部设备通过模块接头提供的信号缓冲到半导体存储器件。 因此，可以减少存储器模块的等待时间。