公开(公告)号：US06784532B2

公开(公告)日：2004-08-31

申请号：US10209847

申请日：2002-07-31

申请人： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

发明人： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

IPC分类号： H01L2352

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

公开(公告)号：US07212395B2

公开(公告)日：2007-05-01

申请号：US11024060

申请日：2004-12-28

申请人： Yuan-Liang Li ,  David G. Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

发明人： Yuan-Liang Li ,  David G. Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

IPC分类号： H01G4/228

CPC分类号： H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01L2224/16 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/0231

摘要： According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

摘要翻译： 根据一些实施例，电容器包括包括第一极性的第一至少一个端子的第一外部电容器平面和包括第一极性的第二至少一个端子的第一内部电容器平面。 第一极性的第二至少一个端子可以电耦合到第一极性的第一至少一个端子，并且第一极性的第二至少一个端子的总面积可以小于第一极性的总面积 第一极性的至少一个端子。

公开(公告)号：US20060139847A1

公开(公告)日：2006-06-29

申请号：US11024060

申请日：2004-12-28

申请人： Yuan-Liang Li ,  David Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

发明人： Yuan-Liang Li ,  David Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

IPC分类号： H01G4/228

CPC分类号： H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01L2224/16 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/0231

摘要： According to some embodiments, a capacitor includes a first external capacitor plane comprising a first at least one terminal of a first polarity, and a first internal capacitor plane comprising a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

摘要翻译： 根据一些实施例，电容器包括包括第一极性的第一至少一个端子和包括第一极性的第二至少一个端子的第一内部电容器平面的第一外部电容器平面。 第一极性的第二至少一个端子可以电耦合到第一极性的第一至少一个端子，并且第一极性的第二至少一个端子的总面积可以小于第一极性的总面积 第一极性的至少一个端子。

公开(公告)号：US07417872B2

公开(公告)日：2008-08-26

申请号：US11459951

申请日：2006-07-26

申请人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

发明人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC分类号： H05H1/11

CPC分类号： H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US07145239B2

公开(公告)日：2006-12-05

申请号：US10977192

申请日：2004-10-29

申请人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

发明人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC分类号： H01L23/48

CPC分类号： H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US06964584B2

公开(公告)日：2005-11-15

申请号：US10032377

申请日：2001-12-21

申请人： Dong Zhong ,  Yuan-Liang Li ,  David G. Figueroa ,  Jiangqi He

发明人： Dong Zhong ,  Yuan-Liang Li ,  David G. Figueroa ,  Jiangqi He

IPC分类号： H01R13/6466 ,  H01R13/6473 ,  H01R13/66

CPC分类号： H01R13/6625 ,  H01R13/6466 ,  H01R13/6473

摘要： The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.

摘要翻译： 本发明涉及一种用于微电子器件的电源插座，其在一个实施例中使用低电阻功率和接地端子配置。 在另一个实施例中，低电阻功率和接地端子配置结合在电源插座上，并具有用于降低电感的垂直取向的交叉指状电容器。 通过该组合，在微电子器件的操作期间实现显着降低的阻抗。 电容器可以包括相对于插座面的主平面垂直定向的板，并且电容器可以位于电源和接地触点之间，两个电源触点之间或两个接地触点之间。

公开(公告)号：US06914334B2

公开(公告)日：2005-07-05

申请号：US10167904

申请日：2002-06-12

申请人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

发明人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC分类号： H01L23/498 ,  H01L23/66 ,  H01P3/08 ,  H05K1/02 ,  H01L23/48

CPC分类号： H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US06995465B2

公开(公告)日：2006-02-07

申请号：US10455908

申请日：2003-06-04

申请人： Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Jung Kang

发明人： Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Jung Kang

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

摘要翻译： 一种装置由集成电路和耦合到集成电路的挠性带构成。 柔性带用于促进/从集成电路进出信号。 在一个实施例中，柔性带包括多个信号迹线。 在另一个实施例中，该装置还包括耦合到柔性带的硅插入件和耦合到硅插入器的衬底。

公开(公告)号：US20060006507A1

公开(公告)日：2006-01-12

申请号：US11228662

申请日：2005-09-15

申请人： Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Jung Kang

发明人： Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Jung Kang

IPC分类号： H01L23/495

CPC分类号： H01L23/50 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal-traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.

摘要翻译： 一种装置由集成电路和耦合到集成电路的挠性带构成。 柔性带用于促进/从集成电路进出信号。 在一个实施例中，柔性带包括多个信号迹线。 在另一个实施例中，该装置还包括耦合到柔性带的硅插入件和耦合到硅插入器的衬底。

公开(公告)号：US06815256B2

公开(公告)日：2004-11-09

申请号：US10329190

申请日：2002-12-23

申请人： David Gregory Figueroa ,  Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Cengiz Ahmet Palanduz

发明人： David Gregory Figueroa ,  Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Cengiz Ahmet Palanduz

IPC分类号： H01L2144

CPC分类号： H01L23/49827 ,  H01L23/481 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/3011 ,  H01L2224/0401

摘要： An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

摘要翻译： 公开了一种改进的硅结构单元。 在一个实施例中，硅结构块具有通过其的至少两个通孔。 硅结构单元被掺杂，并且通孔填充有第一材料，并且可选地，填充了选定的通孔，而不是用第二材料填充。 在替代实施例中，硅积层的区域具有沉积在其上的金属。