公开(公告)号：US20100258820A1

公开(公告)日：2010-10-14

申请号：US12512623

申请日：2009-07-30

申请人： Dong-Gyu KIM ,  Yeong-Keun Kwon ,  Ju-Hee Lee

发明人： Dong-Gyu KIM ,  Yeong-Keun Kwon ,  Ju-Hee Lee

IPC分类号： H01L27/12 ,  G03F1/00 ,  H01L21/336 ,  H01L33/00

CPC分类号： H01L27/1248 ,  G03F1/00 ,  G03F1/36 ,  G03F1/50 ,  H01L27/12 ,  H01L27/124

摘要： A thin film transistor array panel includes a first insulation substrate, a plurality of data wires formed on the first insulation substrate and extending in a first direction, a data pad region formed on the first insulation substrate and having plural ones of the data wires extending therefrom, and an organic layer formed on the data wires, where the organic layer has a greater thickness where it is disposed over the data wires than the thickness it has between the data wires. The surface of the organic layer of the data pad region includes minute slit patterns that extend parallel to the first direction of the data wires, and the data wires have line boundaries of a zigzag shape.

摘要翻译： 薄膜晶体管阵列面板包括第一绝缘基板，形成在第一绝缘基板上并沿第一方向延伸的多条数据线，形成在第一绝缘基板上并具有从其延伸的多条数据线的数据焊盘区域 以及形成在数据线上的有机层，其中有机层的厚度设置在数据线之上，而不是数据线之间的厚度。 数据焊盘区域的有机层的表面包括平行于数据线的第一方向延伸的微细狭缝图案，并且数据线具有之字形形状的线边界。

公开(公告)号：US08334539B2

公开(公告)日：2012-12-18

申请号：US12512623

申请日：2009-07-30

申请人： Dong-Gyu Kim ,  Yeong-Keun Kwon ,  Ju-Hee Lee

发明人： Dong-Gyu Kim ,  Yeong-Keun Kwon ,  Ju-Hee Lee

IPC分类号： H01L33/00

CPC分类号： H01L27/1248 ,  G03F1/00 ,  G03F1/36 ,  G03F1/50 ,  H01L27/12 ,  H01L27/124

摘要： A thin film transistor array panel includes a first insulation substrate, a plurality of data wires formed on the first insulation substrate and extending in a first direction, a data pad region formed on the first insulation substrate and having plural ones of the data wires extending therefrom, and an organic layer formed on the data wires, where the organic layer has a greater thickness where it is disposed over the data wires than the thickness it has between the data wires. The surface of the organic layer of the data pad region includes minute slit patterns that extend parallel to the first direction of the data wires, and the data wires have line boundaries of a zigzag shape.

摘要翻译： 薄膜晶体管阵列面板包括第一绝缘基板，形成在第一绝缘基板上并沿第一方向延伸的多条数据线，形成在第一绝缘基板上并具有从其延伸的多条数据线的数据焊盘区域 以及形成在数据线上的有机层，其中有机层的厚度设置在数据线之上，而不是数据线之间的厚度。 数据焊盘区域的有机层的表面包括平行于数据线的第一方向延伸的微细狭缝图案，并且数据线具有之字形形状的线边界。

公开(公告)号：US09343028B2

公开(公告)日：2016-05-17

申请号：US12423995

申请日：2009-04-15

申请人： Dong-Hyeon Ki ,  Ho-Kyoon Kwon ,  Ju-Hee Lee ,  Byoung-Sun Na

发明人： Dong-Hyeon Ki ,  Ho-Kyoon Kwon ,  Ju-Hee Lee ,  Byoung-Sun Na

IPC分类号： G09G3/36 ,  G11C19/18 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

摘要翻译： 驱动栅极线的方法包括：将扫描开始信号和从前一级提供的进位信号中的一个充电到当前级的第一个节点; 通过在第一节点处拉高高电平的第一时钟信号，通过当前级的门节点输出门信号，以升高第一节点的电压电位; 当第一时钟信号被转换到低电平时，放电第一节点的电压和门节点的电压电位，以将第一节点和门节点保持在第一电源电压; 并且接收前一级的第二节点的电压电位信号，所述第二节点保持从前一级输出的门信号，以减少在第一节点处产生的纹波。

公开(公告)号：US08456409B2

公开(公告)日：2013-06-04

申请号：US12533821

申请日：2009-07-31

申请人： Gwang-Bum Ko ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Ju-Hee Lee ,  Ji-Hyun Kwon

发明人： Gwang-Bum Ko ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Ju-Hee Lee ,  Ji-Hyun Kwon

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0247 ,  G09G2330/06

摘要： Gate drive circuit includes a plurality of stages connected one after another to each other. An m-th stage includes a pull-up section outputting a first clock signal as a gate signal of the m-th stage to an output terminal, a pull-down section applying a low voltage to the output terminal, a carry section outputting the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal, a first carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal and a second carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to a high voltage of the second clock signal.

摘要翻译： 栅极驱动电路包括彼此相继连接的多个级。 第m级包括将作为第m级的门信号的第一时钟信号输出到输出端的上拉部分，向输出端子施加低电压的下拉部分，输出 第一时钟信号作为响应于第一节点信号的高电压的第m级的进位信号，第一进位保持部分响应于高电压而将第m级的进位信号保持在低电压 以及第二进位保持部，其响应于所述第二时钟信号的高电压而将所述第m级的进位信号保持在所述低电压。

公开(公告)号：US20110053292A1

公开(公告)日：2011-03-03

申请号：US12937139

申请日：2009-04-10

申请人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee Lee ,  Kwang-Pyo Kim

发明人： Hyung-Soon Park ,  Sang-Wan So ,  Woon-Seok Yeo ,  Soo-Jae Lee ,  Jung-Rok Lee ,  Ju-Hee Lee ,  Kwang-Pyo Kim

IPC分类号： G01N33/543 ,  C12N9/10 ,  C07K14/435 ,  C07K16/00

CPC分类号： G01N33/553 ,  G01N33/585 ,  G01N33/6848 ,  G01N2458/15 ,  H01J49/00 ,  Y10T436/24

摘要： There is provided a novel method for amplifying mass spectrometric signals. More particularly, a novel method for detecting signals of a target molecule includes: i) allowing a test sample, in which it is required to determine whether or not a target molecule is present, to be contact with a gold particle whose surface is modified to selectively bind to the target molecule, ii) allowing a low molecular molecule engrafted to the gold particle to generate mass spectrometric signals after the interaction, such as binding, between the gold particle and the target molecule, and iii) amplifying the mass spectrometric signals by generating a great deal of mass spectrometric signals of the low molecular molecule even in the presence of a trace of the target molecule. Also, the assay system using the method and the gold particle prepared in the method are provided. The method may be useful to specifically amplify signals of the target molecule without any pretreatment of a test sample, which makes it possible to measure the target molecule simply and precisely.

摘要翻译： 提供了一种扩增质谱信号的新方法。 更具体地，用于检测靶分子的信号的新方法包括：i）允许测试样品，其中需要确定靶分子是否存在，以将其表面修饰的金颗粒与 选择性地结合靶分子，ii）允许移植到金颗粒上的低分子分子在金颗粒和靶分子之间的相互作用之后产生质谱信号，例如结合，以及iii）通过以下步骤扩增质谱信号： 甚至在痕量的靶分子的存在下也产生大量低分子分子的质谱信号。 此外，提供了使用该方法的测定系统和该方法中制备的金颗粒。 该方法可用于特异性扩增靶分子的信号而无需对测试样品进行任何预处理，这使得可以简单且精确地测量目标分子。

公开(公告)号：US20100274003A1

公开(公告)日：2010-10-28

申请号：US12733674

申请日：2008-09-17

申请人： Chang-Seob Kim ,  Dong-Woo Lee ,  Jae-Woo Lee ,  Mi-Ran Jung ,  Young-Cheol Jeong ,  Si-Min Kim ,  Young-Ro Choi ,  Dong-Geun Seo ,  Ju-Hee Lee ,  Phil-Sang Ahn

发明人： Chang-Seob Kim ,  Dong-Woo Lee ,  Jae-Woo Lee ,  Mi-Ran Jung ,  Young-Cheol Jeong ,  Si-Min Kim ,  Young-Ro Choi ,  Dong-Geun Seo ,  Ju-Hee Lee ,  Phil-Sang Ahn

IPC分类号： C07D487/04

CPC分类号： C07D477/20 ,  C07C213/04 ,  C07D205/04 ,  C07C215/08

摘要： The present invention provides a process for preparing an acid addition salt of a synthetic intermediate for carbapenem antibiotics and a novel acid addition salt of a synthetic intermediate for carbapenem antibiotics obtained from the process. The present invention also provides a process for preparing a carbapenem antibiotic using the acid addition salt. According to the process of the present invention, an acid addition salt of a synthetic intermediate for carbapenem antibiotics can be prepared in a high yield and high purity, without conducting column chromatography. Thus, the process of the present invention can be applied to mass production with an industrial scale. Furthermore, since the acid addition salts have solid forms, they are easy to handle and keep in a manufacturing site.

摘要翻译： 本发明提供了一种制备碳青霉烯类抗生素合成中间体的酸加成盐的方法和由该方法得到的碳青霉烯类抗生素合成中间体的新型酸加成盐。 本发明还提供了使用酸加成盐制备碳青霉烯类抗生素的方法。 根据本发明的方法，可以以高产率和高纯度制备碳青霉烯类抗生素合成中间体的酸加成盐，而不进行柱层析。 因此，本发明的方法可以应用于工业规模的批量生产。 此外，由于酸加成盐具有固体形式，因此易于处理并保持在制造现场。

公开(公告)号：US08355090B2

公开(公告)日：2013-01-15

申请号：US12507764

申请日：2009-07-22

申请人： Ji-Hyun Kwon ,  Hye-Seok Na ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Dong-Yoon Lee ,  Ju-Hee Lee ,  Gwang-Bum Ko

发明人： Ji-Hyun Kwon ,  Hye-Seok Na ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Dong-Yoon Lee ,  Ju-Hee Lee ,  Gwang-Bum Ko

IPC分类号： G02F1/1343 ,  G02F1/136

CPC分类号： G02F1/136286 ,  G02F1/134363 ,  G02F2001/134345 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2320/0209

摘要： A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a first pixel formed between the first and second gate lines, the first and the second data lines, a first subpixel configured to have applied thereto a first data voltage and a second subpixel configured to have applied thereto a second data voltage lower than the first data voltage, a second pixel formed between the second and third gate lines, the first and second data lines, and having a third subpixel configured to have applied thereto a third data voltage and a fourth subpixel configured to have applied thereto a fourth data voltage lower than the third data voltage. The first subpixel and the third subpixel are connected to a first thin film transistor and a third thin film transistor respectively, the first thin film transistor and the third thin film transistor have source electrodes connected to the first data line and the second data line respectively, and each of the source electrodes has an open portion surrounding a portion of a drain electrode, and wherein an open direction of the source electrode of the first thin film transistor is opposite to an open direction of the source electrode of the third thin film transistor.

摘要翻译： 根据本发明的示例性实施例的液晶显示器（LCD）包括形成在第一和第二栅极线之间的第一像素，第一和第二数据线，第一子像素，其被配置为向其施加第一数据 电压和第二子像素，其被配置为向其施加低于第一数据电压的第二数据电压;第二像素，形成在第二和第三栅极线之间，第一和第二数据线，并且具有被配置为施加到其的第三子像素 第三数据电压和第四子像素，被配置为向其施加低于第三数据电压的第四数据电压。 第一子像素和第三子像素分别连接到第一薄膜晶体管和第三薄膜晶体管，第一薄膜晶体管和第三薄膜晶体管分别具有连接到第一数据线和第二数据线的源电极， 并且每个源极电极具有围绕漏电极的一部分的开口部分，并且其中第一薄膜晶体管的源极电极的开放方向与第三薄膜晶体管的源电极的开路方向相反。

公开(公告)号：US20100207846A1

公开(公告)日：2010-08-19

申请号：US12607028

申请日：2009-10-27

申请人： Byoung-Sun NA ,  Ju-Hee Lee ,  Won-Hee Lee ,  Ho-Kyoon Kwon

发明人： Byoung-Sun NA ,  Ju-Hee Lee ,  Won-Hee Lee ,  Ho-Kyoon Kwon

IPC分类号： G09G3/20 ,  H01L27/12

CPC分类号： H01L27/124 ,  G02F1/133512 ,  G02F1/13624 ,  G02F2001/134345 ,  H01L27/1218 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/78633 ,  H01L29/78669 ,  H01L29/78678

摘要： Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by a first TFT; a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode; a connecting electrode which is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes; a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode, and blocks light.

摘要翻译： 本公开的实施例提供了一种薄膜晶体管（TFT）面板，其被构造为防止由于背光的亮度变化引起的图像质量的劣化。 根据实施例，TFT面板包括：绝缘基板; 第一栅线和第一数据线，形成在绝缘基板上以彼此绝缘并彼此交叉; 第一子像素电极，其形成在所述绝缘基板上，并且通过第一TFT连接到所述第一栅极线和所述第一数据线; 第二子像素电极，其形成在所述绝缘基板上并与所述第一子像素电极分离; 连接电极，其直接连接到第一和第二子像素电极中的任一个并且电容耦合到第一和第二子像素电极中的另一个; 形成在所述连接电极和所述绝缘基板之间的半导体图案; 并且形成在半导体图案和绝缘基板之间的遮光图案被连接电极重叠，并且阻挡光。

公开(公告)号：US20100201668A1

公开(公告)日：2010-08-12

申请号：US12533821

申请日：2009-07-31

申请人： Gwang-Bum Ko ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Ju-Hee Lee ,  Ji-Hyun Kwon

发明人： Gwang-Bum Ko ,  Won-Hee Lee ,  Ho-Kyoon Kwon ,  Byoung-Sun Na ,  Ju-Hee Lee ,  Ji-Hyun Kwon

IPC分类号： G09G5/00 ,  G09G3/20

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0247 ,  G09G2330/06

摘要： Gate drive circuit includes a plurality of stages connected one after another to each other. An m-th stage includes a pull-up section outputting a first clock signal as a gate signal of the m-th stage to an output terminal, a pull-down section applying a low voltage to the output terminal, a carry section outputting the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal, a first carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal and a second carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to a high voltage of the second clock signal.

摘要翻译： 栅极驱动电路包括彼此相继连接的多个级。 第m级包括将作为第m级的门信号的第一时钟信号输出到输出端的上拉部分，向输出端子施加低电压的下拉部分，输出 第一时钟信号作为响应于第一节点信号的高电压的第m级的进位信号，第一进位保持部分响应于高电压而将第m级的进位信号保持在低电压 以及第二进位保持部，其响应于所述第二时钟信号的高电压而将所述第m级的进位信号保持在所述低电压。