公开(公告)号：US20050009261A1

公开(公告)日：2005-01-13

申请号：US10911157

申请日：2004-08-02

申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

IPC分类号： H01L21/108 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L21/8238

CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

摘要翻译： 提供一种在周边区域具有电阻器的半导体器件及其制造方法。 在半导体基板上形成模层。 图案化模具层以在模具层中形成第一模制孔和第二模制孔。 存储节点层形成在模具层以及第一和第二模制孔中。 存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

公开(公告)号：US07319254B2

公开(公告)日：2008-01-15

申请号：US10911157

申请日：2004-08-02

申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/0392

CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

摘要： A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

摘要翻译： 提供一种在周边区域具有电阻器的半导体器件及其制造方法。 在半导体基板上形成模层。 图案化模具层以在模具层中形成第一模制孔和第二模制孔。 存储节点层形成在模具层以及第一和第二模制孔中。 存储节点层被图案化以在第一成型孔中形成存储节点，并在第二孔中形成电阻器的一部分。

公开(公告)号：US06794247B2

公开(公告)日：2004-09-21

申请号：US10272670

申请日：2002-10-16

申请人： Dong-Hwa Kwak ,  Byung-Seo Kim

发明人： Dong-Hwa Kwak ,  Byung-Seo Kim

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10882 ,  Y10S257/904

摘要： A method of fabricating a semiconductor device having a cell array area and a peripheral circuit area is provided. A mold layer is formed on a substrate in the cell array area and the peripheral circuit area. A plurality of first molding holes are formed in the mold layer in the cell array area. A second molding hole is formed in the mold layer in the peripheral circuit area. A storage node layer is formed on the mold layer, in the first molding holes and in the second molding hole. A plurality of storage nodes are formed in the first molding holes and a first portion of a resistor is formed in the second molding hole by removing a portion of the storage node layer. The first portion of the resistor is formed of the storage node layer.

摘要翻译： 提供一种制造具有单元阵列区域和外围电路区域的半导体器件的方法。 在单元阵列区域和外围电路区域的基板上形成模层。 多个第一成型孔形成在电池阵列区域的模具层中。 在外围电路区域的模具层中形成第二模制孔。 存储节点层形成在模具层上，第一模制孔和第二模制孔中。 多个存储节点形成在第一模制孔中，并且通过去除存储节点层的一部分，在第二模制孔中形成电阻器的第一部分。 电阻器的第一部分由存储节点层形成。

公开(公告)号：US07842571B2

公开(公告)日：2010-11-30

申请号：US11623269

申请日：2007-01-15

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

摘要翻译： 在一个实施例中，半导体器件包括奇数触点和相应的奇数行。 间隔物形成在奇数行的侧壁上，并且通过执行蚀刻工艺形成均匀线的均匀开口。 偶数触点形成在均匀开口中，然后形成均匀的线。

公开(公告)号：US20080057644A1

公开(公告)日：2008-03-06

申请号：US11642198

申请日：2006-12-20

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US20080085581A1

公开(公告)日：2008-04-10

申请号：US11647722

申请日：2006-12-29

申请人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

发明人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

IPC分类号： H01L21/8242

CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/105

摘要： Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.

公开(公告)号：US06288446B1

公开(公告)日：2001-09-11

申请号：US09790642

申请日：2001-02-23

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01G706

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

公开(公告)号：US06218296B1

公开(公告)日：2001-04-17

申请号：US09346922

申请日：1999-07-02

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/90

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

摘要翻译： 一种半导体器件和制造具有与高介电膜兼容的柱状电容器存储节点的半导体器件的方法，其中柱状电容器存储节点包括易于蚀刻的厚导电金属层和完全薄的导电层 涂覆厚的导电金属层。 薄导电层在随后的高介电沉积和退火和各种氧化过程期间保护厚的导电金属层。

公开(公告)号：US07544565B2

公开(公告)日：2009-06-09

申请号：US11642198

申请日：2006-12-20

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L21/8247

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US07521348B2

公开(公告)日：2009-04-21

申请号：US11871877

申请日：2007-10-12

申请人： Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

发明人： Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Dong-Hwa Kwak ,  Joo-Young Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

摘要翻译： 示例性地公开了一种制造具有精细接触孔的半导体器件的方法。 该方法包括在半导体衬底上形成限定有源区的隔离层。 在具有隔离层的半导体衬底上形成层间电介质层。 在层间电介质层上形成第一成型图案。 还形成了位于第一模制图案之间并与之间隔开的第二模制图案。 形成围绕第一和第二模制图案的侧壁的掩模图案。 通过去除第一和第二模制图案形成开口。 通过使用掩模图案作为蚀刻掩模蚀刻层间电介质层来形成接触孔。