公开(公告)号：US20120270376A1

公开(公告)日：2012-10-25

申请号：US13542777

申请日：2012-07-06

申请人： Dongyean Oh ,  Woon-kyung Lee

发明人： Dongyean Oh ,  Woon-kyung Lee

IPC分类号： H01L21/8232

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823493

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US08609496B2

公开(公告)日：2013-12-17

申请号：US13542777

申请日：2012-07-06

申请人： Dongyean Oh ,  Woon-kyung Lee

发明人： Dongyean Oh ,  Woon-kyung Lee

IPC分类号： H01L21/8232

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823493

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US08237230B2

公开(公告)日：2012-08-07

申请号：US12631109

申请日：2009-12-04

申请人： Dongyean Oh ,  Woon-kyung Lee

发明人： Dongyean Oh ,  Woon-kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823493

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US20100140720A1

公开(公告)日：2010-06-10

申请号：US12631109

申请日：2009-12-04

申请人： Dongyean Oh ,  Woon-kyung Lee

发明人： Dongyean Oh ,  Woon-kyung Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823493

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US06448112B2

公开(公告)日：2002-09-10

申请号：US09791938

申请日：2001-02-23

申请人： Woon-kyung Lee

发明人： Woon-kyung Lee

IPC分类号： H01L2182

CPC分类号： H01L27/11266 ,  G11C17/126 ,  H01L27/112 ,  Y10S257/908

摘要： In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

摘要翻译： 在NOR型掩模ROM器件的单元阵列区域及其制造方法中，在半导体衬底上形成彼此平行的多个字线之后，与多个栅极ROM器件的顶部相交的多个子位线 形成直角的字线。 在由多个字线和多个子位线露出的半导体衬底上形成沟槽区域。 在所得材料的整个表面上形成层间绝缘层，并且在层间绝缘层上形成彼此平行的多个位线。

公开(公告)号：US08836020B2

公开(公告)日：2014-09-16

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US07008848B2

公开(公告)日：2006-03-07

申请号：US10713117

申请日：2003-11-17

申请人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

发明人： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

IPC分类号： H01L21/8236

CPC分类号： H01L27/112 ,  H01L27/1126

摘要： A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers. The word lines are formed to be parallel to each other, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to the buried impurity diffusion regions. The pad conductive layers, which form ohmic contacts with the word lines, are formed in an island shape channel regions. These channel regions are defined as the areas between the buried impurity diffusion regions that are overlapped by the word lines.

摘要翻译： 提供了一种掩模只读存储器（ROM）及其制造方法。 该掩模ROM和相关方法能够减少掩埋的杂质扩散区的间距。 在掩模ROM制造工艺中，在半导体衬底上形成栅极绝缘层，并且在栅极绝缘层上形成平行的导电层图案。 这些导电层图案彼此分开第一预定间隔并沿相同的方向延伸。 然后使用导电层图案作为掩模进行离子注入，以在导电层图案之间的半导体衬底附近形成掩埋的杂质扩散区。 然后在所得结构的整个表面上形成用于形成字线的导电层，并且蚀刻导电层和导电层图案，以形成字线和焊盘导电层。 字线形成为彼此平行，彼此分开第二预定间隔，并且在垂直于埋置的杂质扩散区域的方向上延伸。 与字线形成欧姆接触的焊盘导电层形成为岛状沟道区域。 这些沟道区域被定义为由字线重叠的掩埋杂质扩散区域之间的区域。

公开(公告)号：US5920784A

公开(公告)日：1999-07-06

申请号：US933839

申请日：1997-09-19

申请人： Woon-kyung Lee

发明人： Woon-kyung Lee

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8246

CPC分类号： H01L27/11293

摘要： A method for manufacturing a buried transistor, which includes the steps of forming a field oxide layer in a substrate, the field oxide region having a central portion having a greater thickness than opposite edge portions thereof, forming source/drain regions in the substrate, on opposite sides of the field oxide layer, removing the field oxide layer, and forming a gate electrode on the resultant structure.

摘要翻译： 一种埋入晶体管的制造方法，包括以下步骤：在衬底中形成场氧化物层，所述场氧化物区域具有比其相对边缘部分厚的中心部分，在衬底中形成源/漏区，在 场氧化物层的相对侧，去除场氧化物层，并在所得结构上形成栅电极。

公开(公告)号：US08906805B2

公开(公告)日：2014-12-09

申请号：US13418585

申请日：2012-03-13

申请人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

发明人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC分类号： H01L21/768 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

摘要翻译： 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US20120193705A1

公开(公告)日：2012-08-02

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L29/78 ,  H01L23/48

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。