公开(公告)号：US06635936B1

公开(公告)日：2003-10-21

申请号：US09616975

申请日：2000-07-14

申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

IPC分类号： H01L2976

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

公开(公告)号：US6117722A

公开(公告)日：2000-09-12

申请号：US252464

申请日：1999-02-18

申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

IPC分类号： H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90.degree. transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

公开(公告)号：US5926697A

公开(公告)日：1999-07-20

申请号：US947793

申请日：1997-10-09

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

IPC分类号： H01L21/02 ,  H01L21/761 ,  H01L23/525 ,  H01L21/76

CPC分类号： H01L28/87 ,  H01L21/761 ,  H01L23/5258 ,  H01L2924/0002

摘要： An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.

摘要翻译： 已经开发了用于在具有至少一个级别的多晶硅布线的集成电路中形成保护环的改进和新的结构和方法。 保护环形成，而不需要额外的制造工艺步骤，并且保护环结合到半导体衬底，从而为水分和污染物从绝缘层中的窗口扩散到半导体器件区域提供了优越的屏障。

公开(公告)号：US06071798A

公开(公告)日：2000-06-06

申请号：US156361

申请日：1998-09-18

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/768 ,  H01L21/425

CPC分类号： H01L21/0274 ,  H01L21/76895 ,  H01L21/26506

摘要： The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structures 12. A photoresist mask 18A having a buried contact opening 20 is formed over the first conductive layer. The first conductive layer 16 and the first insulating layer 14 are etched through the photoresist mask 18A. A width 21 of the photoresist mask 18A adjacent to the buried contact opening 20 is removed using a descum process, thereby forming an expanded opening 20A and an exposed ring 16A of the first conductive layer 16 with subjacent first insulating layer 14. Impurity ions 23 are implanted through the expanded opening 20A at a sufficient energy level to form a novel buried contact region 22 comprising an extended buried contact region 22A extending under the exposed ring 16A of the first conductive layer 16 and an exposed area 22B where the first conductive layer and the first insulating layer were removed. The photoresist mask 18A is removed. A second conductive layer 24 and a polycide layer 26 are formed over the first conductive layer 16 and over the exposed area 22B of the buried contact region 22. The polycide layer 26, the second conductive layer 24, the first conductive layer 16 and the first insulating layer 14 are patterned to form a second opening 30 partially overlapping the extended buried contact region and defining a gate structure 31 and a contact structure 33. Lightly doped source/drain regions 32, sidewall spacers 34, and source/drain structures 38 are formed.

摘要翻译： 本发明提供一种用于制造在第一导电层16和相​​邻的第一绝缘层14之下延伸的掩埋触点的新方法。在具有隔离结构12的硅衬底10上形成第一绝缘层14和第一导电层。 在第一导电层上形成具有埋入接触开口20的掩模18A。 通过光致抗蚀剂掩模18A蚀刻第一导电层16和第一绝缘层14。 使用除尘工艺去除与掩埋接触开口20相邻的光致抗蚀剂掩模18A的宽度21，从而在第一绝缘层14的下方形成第一导电层16的扩展开口20A和暴露环16A。杂质离子23 通过膨胀的开口20A以足够的能级注入，以形成新颖的埋入接触区域22，其包括在第一导电层16的暴露环16A下面延伸的延伸的掩埋接触区域22A和暴露区域22B，其中第一导电层和 去除第一绝缘层。 去除光致抗蚀剂掩模18A。 在第一导电层16上方和掩埋接触区域22的暴露区域22B之上形成第二导电层24和多晶硅化物层26.多晶硅化物层26，第二导电层24，第一导电层16和第一导电层16 图案化绝缘层14以形成与扩展掩埋接触区域部分重叠并限定栅极结构31和接触结构33的第二开口30。形成轻掺杂的源极/漏极区域32，侧壁间隔物34以及源极/漏极结构38 。

公开(公告)号：US6136633A

公开(公告)日：2000-10-24

申请号：US222272

申请日：1998-12-28

申请人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

发明人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L23/535 ,  H01L27/11 ,  H01L29/78 ,  H01L21/44 ,  H01L21/76 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/743 ,  H01L21/76202 ,  H01L23/535 ,  H01L27/11 ,  H01L29/7833 ,  H01L2924/0002

摘要： A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer having an opening over the planned buried contact. The first polysilicon layer not covered by the photoresist mask is etched away. A portion of the photoresist mask at the edges of the opening is cut away to expose a portion of the first polysilicon layer at the edges of the opening. The gate oxide layer not covered by the mask is etched away using a reduced etching selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening. Ions are implanted through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact. The photoresist mask is removed and a second polysilicon layer is deposited overlying the first polysilicon layer and the buried contact to complete formation of the buried contact.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅氧化层。 第一多晶硅层沉积在栅极氧化物层上。 在第一多晶硅层上形成光致抗蚀剂掩模，该多晶硅层在预定的埋入触点上具有开口。 未被光致抗蚀剂掩模覆盖的第一多晶硅层被蚀刻掉。 在开口的边缘处的光致抗蚀剂掩模的一部分被切除，以在开口的边缘处露出第一多晶硅层的一部分。 使用氧化物对硅的蚀刻选择性降低，掩模未被掩模覆盖的栅极氧化物层被蚀刻掉，使得在开口边缘暴露的第一多晶硅层的上部被蚀刻掉，在边缘处留下较薄的第一多晶硅层 的开幕。 离子通过开口并通过较薄的第一多晶硅层注入到半导体衬底中以形成埋入触点。 去除光致抗蚀剂掩模，并且沉积覆盖第一多晶硅层和埋入触点的第二多晶硅层以完成掩埋触点的形成。

公开(公告)号：US07935994B2

公开(公告)日：2011-05-03

申请号：US11066432

申请日：2005-02-24

申请人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

发明人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

IPC分类号： H01L31/062

CPC分类号： H01L27/14654 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.

摘要翻译： 提供了一种用于为CMOS成像器提供遮光罩的系统和方法。 光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。 该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。

公开(公告)号：US07847847B2

公开(公告)日：2010-12-07

申请号：US11044922

申请日：2005-01-27

申请人： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

发明人： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

摘要： A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

摘要翻译： 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US20100090304A1

公开(公告)日：2010-04-15

申请号：US12626296

申请日：2009-11-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

IPC分类号： H01L31/0232 ,  H01L31/18 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/12 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

摘要翻译： 本公开提供了制造集成电路（IC）的方法。 该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

公开(公告)号：US20080173963A1

公开(公告)日：2008-07-24

申请号：US11626757

申请日：2007-01-24

申请人： Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

发明人： Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

IPC分类号： H01L27/14

CPC分类号： H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

摘要： The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.

摘要翻译： 本公开提供了背面照明半导体器件。 该装置包括具有前表面和后表面的基板; 形成在所述基板中的多个传感器元件，所述多个传感器元件中的每一个被设计和配置成接收朝向所述后表面的光; 以及形成在所述基板中的传感器隔离特征，并且水平地设置在所述多个传感器元件的两个相邻元件之间，并且在所述后表面和所述前表面之间垂直。

公开(公告)号：US20070120160A1

公开(公告)日：2007-05-31

申请号：US11627883

申请日：2007-01-26

申请人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

发明人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Chien-Hsien Tseng ,  Jeng-Shyan Lin

IPC分类号： H01L31/113

CPC分类号： H01L27/14689 ,  H01L27/1463

摘要： Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

摘要翻译： 提供半导体器件及其制造方法。 在一个示例中，该方法包括在嵌入基板中的传感器上形成具有第一折射率的隔离结构。 在隔离结构上形成具有与第一折射率不同的第二折射率的第一层。 从隔离结构的至少一部分去除第一层。 在去除第一层之后，在隔离结构上形成具有第三折射率的第二层。 第三折射率基本上类似于第一折射率。