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    SRAM layout for relaxing mechanical stress in shallow trench isolation technology
    1.
    发明授权
    SRAM layout for relaxing mechanical stress in shallow trench isolation technology 有权
    在浅沟槽隔离技术中放松机械应力的SRAM布局

    公开(公告)号：US06635936B1

    公开(公告)日：2003-10-21

    申请号：US09616975

    申请日：2000-07-14

    申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

    发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

    IPC分类号： H01L2976

    CPC分类号： H01L27/1112 ,  Y10S257/903

    摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

    摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

    SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
    2.
    发明授权
    SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof 有权
    用于在浅沟槽隔离技术中放松机械应力的SRAM布局及其制造方法

    公开(公告)号：US6117722A

    公开(公告)日：2000-09-12

    申请号：US252464

    申请日：1999-02-18

    申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

    发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

    IPC分类号： H01L27/11 ,  H01L21/8234

    CPC分类号： H01L27/1112 ,  Y10S257/903

    摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90.degree. transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

    摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

    Method for fabricating buried contacts
    4.
    发明授权
    Method for fabricating buried contacts 有权
    掩埋触点的制作方法

    公开(公告)号：US06071798A

    公开(公告)日：2000-06-06

    申请号：US156361

    申请日：1998-09-18

    申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

    发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

    IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/768 ,  H01L21/425

    CPC分类号： H01L21/0274 ,  H01L21/76895 ,  H01L21/26506

    摘要： The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structures 12. A photoresist mask 18A having a buried contact opening 20 is formed over the first conductive layer. The first conductive layer 16 and the first insulating layer 14 are etched through the photoresist mask 18A. A width 21 of the photoresist mask 18A adjacent to the buried contact opening 20 is removed using a descum process, thereby forming an expanded opening 20A and an exposed ring 16A of the first conductive layer 16 with subjacent first insulating layer 14. Impurity ions 23 are implanted through the expanded opening 20A at a sufficient energy level to form a novel buried contact region 22 comprising an extended buried contact region 22A extending under the exposed ring 16A of the first conductive layer 16 and an exposed area 22B where the first conductive layer and the first insulating layer were removed. The photoresist mask 18A is removed. A second conductive layer 24 and a polycide layer 26 are formed over the first conductive layer 16 and over the exposed area 22B of the buried contact region 22. The polycide layer 26, the second conductive layer 24, the first conductive layer 16 and the first insulating layer 14 are patterned to form a second opening 30 partially overlapping the extended buried contact region and defining a gate structure 31 and a contact structure 33. Lightly doped source/drain regions 32, sidewall spacers 34, and source/drain structures 38 are formed.

    摘要翻译： 本发明提供一种用于制造在第一导电层16和相​​邻的第一绝缘层14之下延伸的掩埋触点的新方法。在具有隔离结构12的硅衬底10上形成第一绝缘层14和第一导电层。 在第一导电层上形成具有埋入接触开口20的掩模18A。 通过光致抗蚀剂掩模18A蚀刻第一导电层16和第一绝缘层14。 使用除尘工艺去除与掩埋接触开口20相邻的光致抗蚀剂掩模18A的宽度21，从而在第一绝缘层14的下方形成第一导电层16的扩展开口20A和暴露环16A。杂质离子23 通过膨胀的开口20A以足够的能级注入，以形成新颖的埋入接触区域22，其包括在第一导电层16的暴露环16A下面延伸的延伸的掩埋接触区域22A和暴露区域22B，其中第一导电层和 去除第一绝缘层。 去除光致抗蚀剂掩模18A。 在第一导电层16上方和掩埋接触区域22的暴露区域22B之上形成第二导电层24和多晶硅化物层26.多晶硅化物层26，第二导电层24，第一导电层16和第一导电层16 图案化绝缘层14以形成与扩展掩埋接触区域部分重叠并限定栅极结构31和接触结构33的第二开口30。形成轻掺杂的源极/漏极区域32，侧壁间隔物34以及源极/漏极结构38 。

    Trench-free buried contact for locos isolation
    5.
    发明授权
    Trench-free buried contact for locos isolation 有权
    无沟槽埋地接触器用于室内隔离

    公开(公告)号：US6136633A

    公开(公告)日：2000-10-24

    申请号：US222272

    申请日：1998-12-28

    申请人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

    发明人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

    IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L23/535 ,  H01L27/11 ,  H01L29/78 ,  H01L21/44 ,  H01L21/76 ,  H01L21/8234

    CPC分类号： H01L29/6659 ,  H01L21/743 ,  H01L21/76202 ,  H01L23/535 ,  H01L27/11 ,  H01L29/7833 ,  H01L2924/0002

    摘要： A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer having an opening over the planned buried contact. The first polysilicon layer not covered by the photoresist mask is etched away. A portion of the photoresist mask at the edges of the opening is cut away to expose a portion of the first polysilicon layer at the edges of the opening. The gate oxide layer not covered by the mask is etched away using a reduced etching selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening. Ions are implanted through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact. The photoresist mask is removed and a second polysilicon layer is deposited overlying the first polysilicon layer and the buried contact to complete formation of the buried contact.

    摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅氧化层。 第一多晶硅层沉积在栅极氧化物层上。 在第一多晶硅层上形成光致抗蚀剂掩模，该多晶硅层在预定的埋入触点上具有开口。 未被光致抗蚀剂掩模覆盖的第一多晶硅层被蚀刻掉。 在开口的边缘处的光致抗蚀剂掩模的一部分被切除，以在开口的边缘处露出第一多晶硅层的一部分。 使用氧化物对硅的蚀刻选择性降低，掩模未被掩模覆盖的栅极氧化物层被蚀刻掉，使得在开口边缘暴露的第一多晶硅层的上部被蚀刻掉，在边缘处留下较薄的第一多晶硅层 的开幕。 离子通过开口并通过较薄的第一多晶硅层注入到半导体衬底中以形成埋入触点。 去除光致抗蚀剂掩模，并且沉积覆盖第一多晶硅层和埋入触点的第二多晶硅层以完成掩埋触点的形成。

    Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process
    6.
    发明授权
    Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process 有权
    使用额外的硼注入来改善浅沟槽隔离工艺中的NMOS反向窄宽度效应

    公开(公告)号：US5960276A

    公开(公告)日：1999-09-28

    申请号：US161406

    申请日：1998-09-28

    申请人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

    发明人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823878

    摘要： A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions

    摘要翻译： 在NMOS区域中形成具有B掺杂侧壁区域44的浅沟槽隔离（STI）以减小窄有源区12N（例如窄通道区域<0.1μm宽）中的NMOS反向窄宽度效应的方法。 提供具有NMOS区域13和PMOS区域15的衬底。衬底氧化物层20和阻挡层22形成在衬底上。 沟槽24在NMOS和PMOS区域中的衬底10中蚀刻。 蚀刻形成窄的有源区域12N和宽的有源区域12W。 狭窄的有源区域12N具有在0.4和1.0μm之间的宽度。 在衬底上的沟槽的侧壁和底部上生长衬里层30。 形成第一光致抗蚀剂层，覆盖PMOS区域并且在NMOS区域上具有第一开口。 在关键步骤中，在衬底中形成硼掺杂区域44的沟槽的侧壁和底部中进行大角度硼注入。 去除第一光致抗蚀剂层。 绝缘层50形成在NMOS和PMOS区域的沟槽中。 PMOS区域中的PMOS场效应晶体管和NMOS区域中的NMOS场效应晶体管形成。 本发明的硼掺杂区域44减小了NMOS区域中的反向窄的宽效应。

    Method of fabricating an SRAM device with a self-aligned thin film transistor structure
    7.
    发明授权
    Method of fabricating an SRAM device with a self-aligned thin film transistor structure 失效
    制造具有自对准薄膜晶体管结构的SRAM器件的方法

    公开(公告)号：US5674770A

    公开(公告)日：1997-10-07

    申请号：US721664

    申请日：1996-09-27

    申请人： Jin-Yuan Lee ,  Shou-Gwo Wuu

    发明人： Jin-Yuan Lee ,  Shou-Gwo Wuu

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： A process for fabricating SRAM cells, including MOSFET devices, as well as thin film transistor structures, has been developed. The process features self-alignment of the MOSFET polysilicon gate structure to the polysilicon gate structure of the thin film transistor. Self-alignment is accomplished via a photolithographic and dry etching patterning procedure, applied to a combination of polysilicon, and insulator layers, resulting in the desired polysilicon gate structures for both the MOSFET and thin film transistor devices.

    摘要翻译： 已经开发了用于制造包括MOSFET器件以及薄膜晶体管结构的SRAM单元的工艺。 该工艺将MOSFET多晶硅栅极结构的自对准特性与薄膜晶体管的多晶硅栅极结构相结合。 通过光刻和干蚀刻图案化程序实现自对准，施加到多晶硅和绝缘体层的组合，导致用于MOSFET和薄膜晶体管器件的期望的多晶硅栅极结构。