利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

97 条记录 (耗时 0.033 秒)

    Silicon device on Si:C SOI and SiGe and method of manufacture
    3.
    发明授权
    Silicon device on Si:C SOI and SiGe and method of manufacture 有权
    Si：C SOI和SiGe上的硅器件及其制造方法

    公开(公告)号：US08119472B2

    公开(公告)日：2012-02-21

    申请号：US11757883

    申请日：2007-06-04

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

    摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

    摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

    MOSFET with high angle sidewall gate and contacts for reduced miller capacitance
    5.
    发明授权
    MOSFET with high angle sidewall gate and contacts for reduced miller capacitance 有权
    具有高角度侧壁栅极的MOSFET和用于降低铣刀电容的触点

    公开(公告)号：US07224021B2

    公开(公告)日：2007-05-29

    申请号：US11162424

    申请日：2005-09-09

    申请人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Huilong Zhu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

    摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

    摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

    Strained finFETs and method of manufacture
    6.
    发明授权
    Strained finFETs and method of manufacture 有权
    应变finFET和制造方法

    公开(公告)号：US07198995B2

    公开(公告)日：2007-04-03

    申请号：US10733378

    申请日：2003-12-12

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

    摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.

    摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。

    Method of manufacturing strained dislocation-free channels for CMOS
    7.
    发明授权
    Method of manufacturing strained dislocation-free channels for CMOS 有权
    制造用于CMOS的应变无位错通道的方法

    公开(公告)号：US07037770B2

    公开(公告)日：2006-05-02

    申请号：US10687608

    申请日：2003-10-20

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    IPC分类号： H01L21/00

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

    摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

    摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在nFET沟道的沟道中生长SiGe层，并且在pFET沟道中生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配，以在覆盖的生长的外延层中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在另一实施方案中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

    Strained silicon on relaxed sige film with uniform misfit dislocation density
    8.
    发明授权
    Strained silicon on relaxed sige film with uniform misfit dislocation density 有权
    应变硅在轻松的超薄膜上具有均匀的失配位错密度

    公开(公告)号：US06872641B1

    公开(公告)日：2005-03-29

    申请号：US10667603

    申请日：2003-09-23

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    IPC分类号： H01L21/205 ,  C30B1/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/322 ,  H01L21/324 ,  H01L21/36 ,  H01L29/10

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/1054

    摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained layer. During the annealing, interstitial dislocation loops are formed as uniformly tributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

    摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。

    Sidewall semiconductor transistors
    10.
    发明授权
    Sidewall semiconductor transistors 有权
    侧壁半导体晶体管

    公开(公告)号：US07696025B2

    公开(公告)日：2010-04-13

    申请号：US11867840

    申请日：2007-10-05

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

    摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

    摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。