公开(公告)号：US20220181180A1

公开(公告)日：2022-06-09

申请号：US17682235

申请日：2022-02-28

Applicant: EBARA CORPORATION

Inventor： Jumpei Fujikata ,  Yuji Araki ,  Tensei Sato ,  Ryuya Koizumi

IPC: H01L21/67 ,  G05B19/05 ,  C25D3/12 ,  H01L21/677 ,  H01L21/687 ,  G05B23/02 ,  G05B19/418

Abstract: A semiconductor manufacturing apparatus including: a first device; one or more sensors; a first calculation circuit that calculates one or more feature quantities of the first device from the detected physical quantities; and a failure prediction circuit that compares the one or more feature quantities with a plurality of pieces of model data of a temporal change in one or more feature quantities until the first device fails, decides a piece of model data with the minimum difference from the calculated one or more feature quantities among the plurality of pieces of model data, calculates predicted failure time from a difference between a failure point in time and a point in time at which a difference from the calculated one or more feature quantities is the minimum in the piece of model data.

公开(公告)号：US20220222524A1

公开(公告)日：2022-07-14

申请号：US17552835

申请日：2021-12-16

Applicant: EBARA CORPORATION

Inventor： Ryuya Koizumi

IPC: G06N3/08 ,  G06N20/00 ,  G06F30/27 ,  G06F30/392 ,  G06F30/398

Abstract: An optimal number of modules for use is accurately estimated in a semiconductor manufacturing apparatus. Provided is a method applied to a semiconductor manufacturing apparatus including one or a plurality of substrate processing modules each including a plurality of submodules. The present method includes a step of estimating the optimal number of the submodules for use, based on a target production amount and predicted production amount of substrates and a use rate of the substrate processing module, a step of preparing, based on the estimated optimal number for use, a schedule to process a substrate with the optimal number of the submodules for use, a step of updating, based on the prepared schedule, the predicted production amount and the use rate, and a step of repeating the estimating step by use of the updated predicted production amount and use rate, to update the optimal number of the submodules for use.

公开(公告)号：US11315812B2

公开(公告)日：2022-04-26

申请号：US15945487

申请日：2018-04-04

Applicant: EBARA CORPORATION

Inventor： Jumpei Fujikata ,  Yuji Araki ,  Tensei Sato ,  Ryuya Koizumi

IPC: G05B19/05 ,  H01L21/67 ,  G05B23/02 ,  G05B19/418 ,  C25D17/00 ,  C25D21/02 ,  C25D21/12 ,  H01L21/677 ,  C25D3/12 ,  H01L21/687 ,  C25D17/10 ,  C25D21/06 ,  C25D17/02 ,  C25D21/10

Abstract: Provided is a semiconductor manufacturing apparatus, comprising: a first device; one or more sensors that detect physical quantities indicating a state of the first device; a first calculation circuit that calculates one or more feature quantities of the first device from the detected physical quantities; and a failure prediction circuit that monitors a temporal change in the one or more feature quantities calculated in the first calculation circuit, and stops receiving a new substrate when a duration for which a degree of deviation of the one or more feature quantities from those at a normal time is increasing exceeds a first time, and/or when a number of increases and decreases per unit time in the degree of deviation of the one or more feature quantities from those at the normal time exceeds a first number.

公开(公告)号：US20210011462A1

公开(公告)日：2021-01-14

申请号：US17036189

申请日：2020-09-29

Applicant: EBARA CORPORATION

Inventor： Koji Nonobe ,  Takashi Mitsuya ,  Ryuya Koizumi ,  Kunio Oishi

IPC: G05B19/4155 ,  H01L21/677 ,  G05B19/418 ,  H01L21/67

Abstract: A calculation amount and calculation time for a substrate conveyance schedule are reduced. A scheduler is provided which is incorporated in a control section of a substrate processing apparatus including a plurality of substrate processing sections that process a substrate, a conveyance section that conveys the substrate, and the control section that controls the conveyance section and the substrate processing sections, and calculates a substrate conveyance schedule. The scheduler includes: a modeling section that models processing conditions, processing time and constraints of the substrate processing apparatus into nodes and edges using a graph network theory, prepares a graph network, and calculates a longest route length to each node; and a calculation section that calculates the substrate conveyance schedule based on the longest route length.

公开(公告)号：US12054841B2

公开(公告)日：2024-08-06

申请号：US17895558

申请日：2022-08-25

Applicant: EBARA CORPORATION

Inventor： Kazuma Ideguchi ,  Hideki Wakabayashi ,  Ryuya Koizumi

IPC: C25D21/12 ,  C25D5/02 ,  C25D17/00

CPC classification number: C25D21/12 ,  C25D5/022 ,  C25D17/001 ,  C25D17/008

Abstract: One object of the present disclosure is to improve the accuracy of detection of an abnormality of various devices, and/or to advance the timing of detection of an abnormality. There is provided an apparatus for plating a substrate, comprising: an anode placed to be opposed to the substrate; an electric field regulating member placed between the substrate and the anode, provided with an opening, and equipped with an opening adjustment member configured to change a dimension of the opening; a motor configured to drive the opening adjustment member; and a control device configured to obtain an electric current value or a load factor of the motor, to calculate an amount of change in the load factor of the motor per unit time from the obtained electric current value or the obtained load factor of the motor, and to detect an abnormality of the electric field regulating member when it is detected that the amount of change in the load factor of the motor per unit time exceeds a predetermined threshold value.

公开(公告)号：US11099546B2

公开(公告)日：2021-08-24

申请号：US17036189

申请日：2020-09-29

Applicant: EBARA CORPORATION

Inventor： Koji Nonobe ,  Takashi Mitsuya ,  Ryuya Koizumi ,  Kunio Oishi

IPC: H01L21/677 ,  G05B19/418 ,  G05B19/4155 ,  H01L21/67

Abstract: A calculation amount and calculation time for a substrate conveyance schedule are reduced. A scheduler is provided which is incorporated in a control section of a substrate processing apparatus including a plurality of substrate processing sections that process a substrate, a conveyance section that conveys the substrate, and the control section that controls the conveyance section and the substrate processing sections, and calculates a substrate conveyance schedule. The scheduler includes: a modeling section that models processing conditions, processing time and constraints of the substrate processing apparatus into nodes and edges using a graph network theory, prepares a graph network, and calculates a longest route length to each node; and a calculation section that calculates the substrate conveyance schedule based on the longest route length.

公开(公告)号：US10824135B2

公开(公告)日：2020-11-03

申请号：US15868753

申请日：2018-01-11

Applicant: EBARA CORPORATION

Inventor： Koji Nonobe ,  Takashi Mitsuya ,  Ryuya Koizumi ,  Kunio Oishi

IPC: G05B19/4155 ,  H01L21/677 ,  G05B19/418 ,  H01L21/67

Abstract: A calculation amount and calculation time for a substrate conveyance schedule are reduced. A scheduler is provided which is incorporated in a control section of a substrate processing apparatus including a plurality of substrate processing sections that process a substrate, a conveyance section that conveys the substrate, and the control section that controls the conveyance section and the substrate processing sections, and calculates a substrate conveyance schedule. The scheduler includes: a modeling section that models processing conditions, processing time and constraints of the substrate processing apparatus into nodes and edges using a graph network theory, prepares a graph network, and calculates a longest route length to each node; and a calculation section that calculates the substrate conveyance schedule based on the longest route length.

公开(公告)号：US20200232115A1

公开(公告)日：2020-07-23

申请号：US16842423

申请日：2020-04-07

Applicant: EBARA CORPORATION

Inventor： Ryuya Koizumi ,  Masashi Shimoyama ,  Mizuki Nagai

IPC: C25D21/14 ,  C25D21/12 ,  C25D17/02 ,  C25D17/06 ,  C25D17/00 ,  H01L21/67

Abstract: A plating method capable of saving a substrate in an event of a failure of a transporter, a plating tank, or other component when the substrate is being plated is disclosed. The plating method includes: transporting a plurality of substrates to a plurality of plating tanks, respectively, with a transporter; immersing the plurality of substrates in a plating solution held in the plurality of plating tanks to plate the plurality of substrates; detecting a failure that has occurred in the transporter or a post-processing tank; and replacing the plating solution in the plurality of plating tanks with a preservative liquid to thereby immerse the plurality of substrates in the preservative liquid.

公开(公告)号：US10446422B2

公开(公告)日：2019-10-15

申请号：US15941760

申请日：2018-03-30

Applicant: EBARA CORPORATION

Inventor： Masayuki Fujiki ,  Hideharu Aoyama ,  Ryuya Koizumi

IPC: G06F3/0484 ,  H01L21/67 ,  C25D17/00 ,  G06F3/147 ,  G05B19/46 ,  C25D21/12 ,  G06T13/80

Abstract: A method is provided, the method including: repeatedly acquiring a state of one or more devices included in the semiconductor manufacturing apparatus; providing a first animation indicating an operation of the semiconductor manufacturing apparatus by displaying at least an image indicating the state of one or more devices on a display unit each time the state is acquired; storing, in a memory, the acquired state of one or more devices and a time related to the state; receiving an input for switching a display mode; and providing a second animation of the semiconductor manufacturing apparatus by displaying, one by one on the display unit, at least one or more images respectively indicating the state of one or more devices related to one or more times including a reference time stored in the memory, after receiving the input for switching a display mode.

公开(公告)号：US12191178B2

公开(公告)日：2025-01-07

申请号：US17682235

申请日：2022-02-28

Applicant: EBARA CORPORATION

Inventor： Jumpei Fujikata ,  Yuji Araki ,  Tensei Sato ,  Ryuya Koizumi

IPC: H01L21/67 ,  C25D3/12 ,  G05B19/05 ,  G05B19/418 ,  G05B23/02 ,  H01L21/677 ,  H01L21/687 ,  C25D17/00 ,  C25D17/02 ,  C25D17/10 ,  C25D21/06 ,  C25D21/10 ,  C25D21/12

Abstract: A semiconductor manufacturing apparatus including: a first device; a first calculation circuit that calculates one or more feature quantities of the first device from detected physical quantities; and a failure prediction circuit that determines a portion of model data with a minimum deviation between the measured feature quantities vector comprising the measured one or more feature quantities and a feature quantities vector comprising one or more feature quantities at each time in the plurality of pieces of model data, and calculates a predicted time until failure from a difference between the failure time point in the determined piece of model data and a point in time in the determined piece of model data at which the deviation between the measured feature quantities vector and the feature quantities vector at each time of the plurality of portions of model data is the minimum; and stops the receiving of a new substrate to prevent an introduction of defects on the new substrate.