公开(公告)号：US20150236169A1

公开(公告)日：2015-08-20

申请号：US14704300

申请日：2015-05-05

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBON

发明人： Sang Hee PARK ,  Chi Sun HWANG ,  Chun Won BYUN ,  Elvira M.C. FORTUNATO ,  Rodrigo F.P. MARTINS ,  Ana R.X. BARROS ,  Nuno F.O. CORREIA ,  Pedro M.C. BARQUINHA ,  Vitor M.L. FIGUEIREDO

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC分类号： H01L29/78693 ,  C23C14/08 ,  C23C14/086 ,  C23C14/087 ,  H01L21/02422 ,  H01L21/02565 ,  H01L21/02579 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02631 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/24 ,  H01L29/242 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/94

摘要： Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.

摘要翻译： 提供一种使用p型氧化物半导体层的半导体器件及其制造方法。 该装置包括由至少一种氧化物形成的p型氧化物层，所述氧化物选自由含铜（Cu）的一氧化碳，含锡（Sn）的一氧化锡，含有Cu-Sn的铜锡氧化物 合金和含有Ni-Sn合金的镍锡氧化物。 因此，使用p型氧化物层容易显影透明或不透明的装置。 由于使用低温工艺形成的氧化物层被应用于半导体器件，所以可以简化半导体器件的制造工艺，并且可以降低制造成本。

公开(公告)号：US20140042539A1

公开(公告)日：2014-02-13

申请号：US13960352

申请日：2013-08-06

申请人： Electronics and Telecommunications Research Institute

发明人： Chi Sun HWANG ,  Sang Hee PARK ,  Him Chan OH

IPC分类号： H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

摘要： Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.

摘要翻译： 公开了一种在具有自对准结构的薄膜晶体管中使用掺杂阻挡层控制掺杂材料的扩散长度的自对准薄膜晶体及其制造方法。 具有掺杂势垒的自对准薄膜晶体管包括：形成在衬底上并具有第一掺杂区，第二掺杂区和沟道区的有源层; 形成在沟道区上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述第一掺杂区域和所述第二掺杂区域上的掺杂源膜; 以及在掺杂源膜和第一掺杂区之间以及在掺杂源膜和第二掺杂区之间形成的掺杂势垒。

公开(公告)号：US20140035621A1

公开(公告)日：2014-02-06

申请号：US14049800

申请日：2013-10-09

申请人： Konkuk University Industrial Cooperation Corp ,  ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Sang Hee PARK ,  Chi Sun HWANG ,  Sung MIN Yoon ,  Him Chan OH ,  Kee Chan PARK ,  Tao REN ,  Hong Kyun LEEM ,  Min Woo OH ,  Ji Sun KIM ,  Jae Eun PI ,  Byeong Hoon KIM ,  Byoung Gon YU

IPC分类号： H03K3/012

CPC分类号： H03K3/012 ,  H03K19/094 ,  H03K19/20

摘要： Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

摘要翻译： 公开了一种逆变器，NAND门和NOR门。 逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。

公开(公告)号：US20130189816A1

公开(公告)日：2013-07-25

申请号：US13792436

申请日：2013-03-11

申请人： Electronics and Telecommunications Research Institute

发明人： Min Ki RYU ,  Chi Sun HWANG ,  Chun Won BYUN ,  Hye Yong CHU ,  Kyoung Ik CHO

IPC分类号： H01L29/786

CPC分类号： H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

摘要： A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US20160104804A1

公开(公告)日：2016-04-14

申请号：US14971217

申请日：2015-12-16

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Him Chan OH ,  Chi Sun HWANG ,  Sang Hee PARK

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/24

CPC分类号： H01L29/78696 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

摘要翻译： 本发明公开了一种自对准薄膜晶体管及其制造方法，其能够同时提高操作速度和稳定性，并且通过形成源极和漏极以自对准地使其尺寸最小化。 根据本公开的示例性实施例的制造薄膜晶体管的方法包括：在衬底上形成有源层，栅极绝缘体和栅极层; 形成用于限定所述栅极层上的栅电极的形状的光致抗蚀剂层图案; 通过使用光致抗蚀剂层图案蚀刻栅极层，栅极绝缘体和有源层; 通过具有方向性的沉积方法在蚀刻的衬底上沉积源极和漏极层; 以及通过去除光致抗蚀剂层图案形成栅电极和自对准源电极和漏电极。

公开(公告)号：US20140011297A1

公开(公告)日：2014-01-09

申请号：US14022705

申请日：2013-09-10

申请人： Electronics and Telecommunications Research Institute

发明人： Sung Min YOON ,  Chun Won BYUN ,  Shin Hyuk YANG ,  Sang Hee PARK ,  Soon Won JUNG ,  Seung Youl KANG ,  Chi Sun HWANG ,  Byoung Gon YU

IPC分类号： H01L29/66

CPC分类号： H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

摘要： Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

摘要翻译： 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。

公开(公告)号：US20130302923A1

公开(公告)日：2013-11-14

申请号：US13908009

申请日：2013-06-03

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Sang Hee PARK ,  Chi Sun HWANG ,  Byoung Gon YU

IPC分类号： H01L51/52

CPC分类号： H01L51/5284 ,  H01L27/1218 ,  H01L27/322 ,  H01L27/326 ,  H01L29/78633 ,  H01L29/7869

摘要： Disclosed are an active matrix organic light emitting diode and a method for manufacturing the same. The active matrix organic light emitting diode includes: a substrate; a black matrix formed above a part of the substrate; at least one thin film transistor formed above the black matrix; a passivation film formed to entirely cover the at least one thin film transistor; a planarizing layer formed above the passivation film; a color filter formed above an upper part of the planarizing layer opposite to the position where the at least one thin film transistor is formed; and an organic light emitting diode formed above the color filter.

摘要翻译： 公开了有源矩阵有机发光二极管及其制造方法。 有源矩阵有机发光二极管包括：基板; 形成在基板的一部分上方的黑色矩阵; 形成在黑矩阵上方的至少一个薄膜晶体管; 形成为完全覆盖所述至少一个薄膜晶体管的钝化膜; 形成在钝化膜上方的平坦化层; 形成在所述平坦化层的与形成有所述至少一个薄膜晶体管的位置相反的上方的滤色器; 以及形成在滤色器上方的有机发光二极管。

公开(公告)号：US20140042475A1

公开(公告)日：2014-02-13

申请号：US13960413

申请日：2013-08-06

申请人： Electronics and Telecommunications Research Institute

发明人： Sang Hee PARK ,  Chi Sun HWANG

IPC分类号： H01L27/32

CPC分类号： H01L27/3267 ,  G02F1/133553 ,  G02F2001/133626 ,  H01L51/5271

摘要： Disclosed is a dual display device having a vertical structure, in which a reflective display device and a self-emissive display device are formed on one substrate in a vertical structure so as to enable a reflective display or a self-emissive display according to a situation and provide a high resolution display. The dual display device having a vertical structure includes: a thin film transistor formed on a substrate; a white light emitting device formed on the thin film transistor: a reflection adjusting layer formed on the white light emitting device; and a color converting layer formed on the reflection adjusting layer.

摘要翻译： 公开了一种具有垂直结构的双显示装置，其中反射显示装置和自发光显示装置以垂直结构形成在一个基板上，以便能够根据情况进行反射显示或自发显示 并提供高分辨率显示。 具有垂直结构的双显示装置包括：形成在基板上的薄膜晶体管; 形成在所述薄膜晶体管上的白色发光器件，形成在所述白色发光器件上的反射调节层; 以及形成在反射调节层上的颜色转换层。

公开(公告)号：US20130161732A1

公开(公告)日：2013-06-27

申请号：US13712428

申请日：2012-12-12

申请人： Electronics and Telecommunications Research Institute

发明人： Chi Sun HWANG ,  Sang Hee Park

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/41733 ,  H01L29/78642

摘要： Disclosed is a vertical channel thin film transistor including a substrate; a drain electrode formed on the substrate; a spacer formed on the substrate while coming into contact with the drain electrode; a source electrode formed on the spacer; an active layer formed on an entire surface of the substrate including the drain electrode and the source electrode and configured to form a vertical channel; a gate insulating layer formed on the active layer; and a gate electrode formed on the gate insulating layer.

摘要翻译： 公开了一种包括衬底的垂直沟道薄膜晶体管; 形成在所述基板上的漏电极; 在与所述漏电极接触的同时在所述基板上形成的间隔物; 形成在间隔物上的源电极; 形成在包括所述漏电极和所述源电极的所述基板的整个表面上的有源层，并且被构造成形成垂直沟道; 形成在所述有源层上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。