公开(公告)号：US20220223696A1

公开(公告)日：2022-07-14

申请号：US17574271

申请日：2022-01-12

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae Kyoung MUN ,  Woojin CHANG ,  Yoo Jin JANG ,  Kyu Jun CHO

IPC: H01L29/40 ,  H01L21/02

Abstract: Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer.

公开(公告)号：US20190081166A1

公开(公告)日：2019-03-14

申请号：US16028612

申请日：2018-07-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae Won DO ,  Dong Min KANG ,  Dong-Young KIM ,  SEONG-IL KIM ,  Hae Cheon KIM ,  Byoung-Gue MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  Jongmin LEE ,  Jong-Won LIM ,  Sungjae CHANG ,  Yoo Jin JANG ,  Hyunwook JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/205

Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.

公开(公告)号：US20180145684A1

公开(公告)日：2018-05-24

申请号：US15654792

申请日：2017-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin CHANG ,  Jong-Won LIM ,  Dong Min KANG ,  Dong-Young KIM ,  Seong-il KIM ,  Hae Cheon KIM ,  Jae Won DO ,  BYOUNG-GUE MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  JONGMIN LEE ,  Sungjae CHANG ,  Yoo Jin JANG ,  HYUNWOOK JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC: H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353

CPC classification number: H03K17/687 ,  G11C5/14 ,  H03K3/353 ,  H03K17/08122 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145 ,  H03K17/162 ,  H03K17/28 ,  H03K17/693 ,  H03K19/0175

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

公开(公告)号：US20170237171A1

公开(公告)日：2017-08-17

申请号：US15229891

申请日：2016-08-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Dong-Young KIM ,  Dong Min KANG ,  SEONG-IL KIM ,  Hae Cheon KIM ,  Jae Won DO ,  Byoung-Gue MIN ,  Ho Kyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  Jong Min LEE ,  Jong-Won LIM ,  Yoo Jin JANG ,  Hyun Wook JUNG ,  Kyu Jun CHO ,  Chull Won JU

IPC: H01Q9/04 ,  H01Q1/50

CPC classification number: H01Q9/0407 ,  H01Q1/50 ,  H01Q9/0442

Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.