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公开(公告)号：US20130293295A1
公开(公告)日：2013-11-07
申请号：US13832452
申请日：2013-03-15
Inventor： Youn Sub NOH , In Bok YOM , Dong Pil CHANG , Hong Gu JI
IPC: H03F3/60
CPC classification number: H03F3/602 , H03F1/0288 , H03F2200/192
Abstract: Provided is a compact RF power amplifier including: a Doherty amplifier comprising a carrier amplifier comprising a first input impedance matching unit, a first amplifier, and a first output impedance matching unit, and a peaking amplifier comprising a second input impedance matching unit, a second amplifier, and a second output impedance matching unit, in which when a power level of the first RF amplified signal reaches a predetermined power level, the peaking amplifier outputs the second RF amplified signal.
Abstract translation: 提供了一种紧凑的RF功率放大器，包括：Doherty放大器，包括载波放大器，该载波放大器包括第一输入阻抗匹配单元，第一放大器和第一输出阻抗匹配单元，以及峰值放大器，包括第二输入阻抗匹配单元， 放大器和第二输出阻抗匹配单元，其中当第一RF放大信号的功率电平达到预定功率电平时，峰值放大器输出第二RF放大信号。
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公开(公告)号：US20130277717A1
公开(公告)日：2013-10-24
申请号：US13867338
申请日：2013-04-22
Inventor： Hong Gu JI , In Bok YOM
IPC: H01L29/06
CPC classification number: H01L29/0653 , H01L23/4821 , H01L23/4824 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
Abstract: A switch device using a frequency control device having an improved isolation feature is provided. The switch device may include a transmission line comprising an input terminal and an output terminal, and a frequency control device to switch a frequency input to the input terminal so that the frequency is selectively transferred to the output terminal. The transmission line may be formed in the form of an air bridge, in an upper portion of the frequency control device.
Abstract translation: 提供一种使用具有改进的隔离特征的频率控制装置的开关装置。 开关装置可以包括输入端子和输出端子的传输线，以及频率控制装置，用于将频率输入切换到输入端子，使得频率被选择性地传送到输出端子。 传输线可以以空气桥的形式形成在频率控制装置的上部。
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公开(公告)号：US20230115787A1
公开(公告)日：2023-04-13
申请号：US17879047
申请日：2022-08-02
Inventor： Hong Gu JI , Dong Min KANG , BYOUNG-GUE MIN , JONGMIN LEE , Kyu Jun CHO
IPC: H03K17/687
Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
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公开(公告)号：US20150137907A1
公开(公告)日：2015-05-21
申请号：US14535476
申请日：2014-11-07
Inventor： Hong Gu JI , In Kwon JU , In Bok YOM
IPC: H01P5/18
CPC classification number: H01P5/185
Abstract: Provided is a directional coupler having high isolation, the directional coupler including a first directional coupler including a first main line and a first sub-line, and a second directional coupler including a second main line and a second sub-line, wherein the first directional coupler is connected to the second directional coupler in series.
Abstract translation: 提供了一种具有高隔离度的定向耦合器，所述定向耦合器包括包括第一主线和第一子线的第一定向耦合器以及包括第二主线和第二子线的第二定向耦合器，其中所述第一定向耦合器 耦合器串联连接到第二定向耦合器。
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公开(公告)号：US20150137877A1
公开(公告)日：2015-05-21
申请号：US14308931
申请日：2014-06-19
Inventor： Yun Ho CHOI , Youn Sub NOH , Hong Gu JI , Jin Cheol JEONG , In Bok YOM
IPC: G05F3/16
Abstract: Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.
Abstract translation: 提供偏置电路。 偏置电路包括：连接在接地端子和第一节点之间的第一电阻器; 具有连接到第一节点的漏极和连接到第二节点的源极的第一偏置晶体管; 具有连接到第二节点的漏极和连接到负电压端子的源极的第二偏置晶体管; 具有连接到所述接地端子的漏极和连接到第三节点的源极的第三偏置晶体管; 以及连接在所述第三节点和所述负电压端子之间的第二电阻器，其中所述第一偏置晶体管的栅极连接到所述第二节点; 第二偏置晶体管的栅极连接到负电压端子; 第三偏置晶体管的栅极连接到第一节点; 并且通过第三节点输出栅极偏置电压信号。
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Patent Agency Ranking
公开(公告)号：US20130278332A1
公开(公告)日：2013-10-24
申请号：US13793164
申请日：2013-03-11
Inventor： Hong Gu JI , In Bok YOM
IPC: H03F1/32
CPC classification number: H03F1/3241 , H03F1/0288 , H03F1/3276
Abstract: Disclosed is a Doherty amplifying apparatus and method that ensures efficiency in linearity of an input signal by linearizing an applied signal using a linearization unit by analog pre-distortion, and amplifying the linearized signal using a primary amplifier and a secondary amplifier.
Abstract translation: 公开了通过使用线性化单元通过模拟预失真线性化施加的信号并且使用主放大器和次级放大器来放大线性化信号来确保输入信号的线性度的效率的Doherty放大装置和方法。
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公开(公告)号：US20230142553A1
公开(公告)日：2023-05-11
申请号：US17886061
申请日：2022-08-11
Inventor： Woojin CHANG , Dong Min KANG , BYOUNG-GUE MIN , JONG YUL PARK , JONGMIN LEE , YOO JIN JANG , KYU JUN CHO , Hong Gu JI
Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.
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公开(公告)号：US20190103483A1
公开(公告)日：2019-04-04
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun AHN , Min Jeong SHIN , Jeong Jin KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Hyung Seok LEE , Jong-Won LIM , Sungjae CHANG , Hyunwook JUNG , Kyu Jun CHO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE , Hong Gu JI
IPC: H01L29/78 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/3065
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US20190081166A1
公开(公告)日：2019-03-14
申请号：US16028612
申请日：2018-07-06
Inventor： Jae Won DO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Byoung-Gue MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jongmin LEE , Jong-Won LIM , Sungjae CHANG , Yoo Jin JANG , Hyunwook JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/205
Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
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公开(公告)号：US20180145684A1
公开(公告)日：2018-05-24
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin CHANG , Jong-Won LIM , Dong Min KANG , Dong-Young KIM , Seong-il KIM , Hae Cheon KIM , Jae Won DO , BYOUNG-GUE MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , JONGMIN LEE , Sungjae CHANG , Yoo Jin JANG , HYUNWOOK JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353
CPC classification number: H03K17/687 , G11C5/14 , H03K3/353 , H03K17/08122 , H03K17/102 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/28 , H03K17/693 , H03K19/0175
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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