公开(公告)号：US20150206847A1

公开(公告)日：2015-07-23

申请号：US14453969

申请日：2014-08-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hae Cheon KIM ,  Ho Kyun AHN ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Jong Won LIM

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0225 ,  H01L2224/03466 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1423 ,  H01L2924/201 ,  H01L2924/37001 ,  H01L2224/45099

Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.

Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。

公开(公告)号：US20140213045A1

公开(公告)日：2014-07-31

申请号：US14230031

申请日：2014-03-31

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Bum BAE ,  Eun Soo NAM ,  Jae Kyoung MUN ,  Sung Bock KIM ,  Hae Cheon KIM ,  Chull Won JU ,  Sang Choon KO ,  Jong-Won LIM ,  Ho Kyun AHN ,  Woo Jin CHANG ,  Young Rak PARK

IPC: H01L29/66

CPC classification number: H01L29/66446 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0883

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。

公开(公告)号：US20150380482A1

公开(公告)日：2015-12-31

申请号：US14658121

申请日：2015-03-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ho Kyun AHN ,  Hae Cheon KIM ,  Jong Won LIM ,  Dong Min KANG ,  Yong Hwan KWON ,  SEONG IL KIM ,  Zin Sig KIM ,  Eun Soo NAM ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Kyung Ho LEE ,  Jong Min LEE ,  Kyu Jun CHO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/31 ,  H01L29/778 ,  H01L29/45

CPC classification number: H01L21/28264 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

Abstract translation: 本文提供了包括基板的半导体器件; 形成在所述基板的顶部上的有源层; 形成在所述有源层的顶部上并具有第一孔的保护层; 源电极，形成在保护层顶部的驱动栅电极和漏电极; 以及形成在所述第一孔的顶部上的第一附加栅电极，其中由于施加到所述源电极，漏电极和驱动栅电极中的每一个的电压，向所述有源层，保护层和驱动栅电极施加电场， 并且第一附加栅电极被配置为衰减施加到有源层，保护层和驱动栅电极的至少一部分的电场的尺寸。

公开(公告)号：US20150194494A1

公开(公告)日：2015-07-09

申请号：US14243322

申请日：2014-04-02

Applicant: Electronics and Telecommunications Research Institute

Inventor： Ho Kyun AHN ,  Hae Cheon KIM ,  Zin Sig KIM ,  Sang Heung LEE ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Dong Min KANG ,  Seong Il KIM ,  Jong Min LEE ,  Jong Won LIM ,  Yong Hwan KWON ,  Eun Soo NAM

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/402 ,  H01L21/283 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787

Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.

Abstract translation: 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。

公开(公告)号：US20170236909A1

公开(公告)日：2017-08-17

申请号：US15248676

申请日：2016-08-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ho Kyun AHN ,  Dong Min KANG ,  Yong-Hwan KWON ,  Dong-Young KIM ,  SEONG IL KIM ,  Hae Cheon KIM ,  Eun Soo NAM ,  Jae Won DO ,  Byoung-Gue MIN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  Jong Min LEE ,  Jong-Won LIM ,  Hyun Wook JUNG ,  Kyu Jun CHO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/404 ,  H01L21/6835 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.

公开(公告)号：US20170133471A1

公开(公告)日：2017-05-11

申请号：US15238492

申请日：2016-08-16

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jong Min LEE ,  Byoung-Gue MIN ,  Hyung Sup YOON ,  Dong Min KANG ,  Dong-Young KIM ,  SEONG-IL KIM ,  Hae Cheon KIM ,  Jae Won DO ,  Ho Kyun AHN ,  Sang-Heung LEE ,  Jong-Won LIM ,  Hyun Wook JUNG ,  Kyu Jun CHO ,  Chull Won JU

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.

公开(公告)号：US20150129890A1

公开(公告)日：2015-05-14

申请号：US14583858

申请日：2014-12-29

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hokyun AHN ,  Jong-Won LIM ,  Jeong-Jin KIM ,  Hae Cheon KIM ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。

公开(公告)号：US20230054026A1

公开(公告)日：2023-02-23

申请号：US17891832

申请日：2022-08-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hyun Wook JUNG ,  Seong II KIM ,  Hae Cheon KIM ,  Youn Sub NOH ,  Ho Kyun AHN ,  Sang Heung LEE ,  Jong Won LIM ,  Sung Jae CHANG ,  II Gyu CHOI

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40

Abstract: Provided are a nitride-based high electron mobility transistor having enhanced frequency characteristics and an improved structural stability and manufacturing method thereof. The nitride-based high electron mobility transistor includes a first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, source drain electrodes formed on the second semiconductor layer, a first insulating film formed on the second semiconductor layer and having an opening, a dielectric formed on the first insulating film to surround the opening of the first insulating film, a second insulating film formed on an inner sidewall of the dielectric, and a gate electrode formed on the dielectric to fill the opening of the first insulating film and inside the inner sidewall of the dielectric. A width of the inner sidewall at a bottom end of the dielectric is smaller than a width of the inner sidewall at a top end of the dielectric.

公开(公告)号：US20220285244A1

公开(公告)日：2022-09-08

申请号：US17562587

申请日：2021-12-27

Applicant: Electronics and Telecommunications Research Institute

Inventor： Il Gyu CHOI ,  Seong Il KIM ,  Hae Cheon KIM ,  Youn Sub NOH ,  Ho Kyun AHN ,  Sang Heung LEE ,  Jong Won LIM ,  Sung Jae CHANG ,  Hyun Wook JUNG

IPC: H01L23/373

Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.

公开(公告)号：US20190103483A1

公开(公告)日：2019-04-04

申请号：US16137235

申请日：2018-09-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hokyun AHN ,  Min Jeong SHIN ,  Jeong Jin KIM ,  Hae Cheon KIM ,  Jae Won DO ,  Byoung-Gue MIN ,  Hyung Sup YOON ,  Hyung Seok LEE ,  Jong-Won LIM ,  Sungjae CHANG ,  Hyunwook JUNG ,  Kyu Jun CHO ,  Dong Min KANG ,  Dong-Young KIM ,  SEONG-IL KIM ,  Sang-Heung LEE ,  Jongmin LEE ,  Hong Gu JI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3065

Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.