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公开(公告)号：US20150087142A1
公开(公告)日：2015-03-26
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won LIM , Ho Kyun AHN , Young Rak PARK , Dong Min KANG , Woo Jin CHANG , Seong-il KIM , Sung Bum BAE , Sang-Heung LEE , Hyung Sup YOON , Chull Won JU , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L29/66 , H01L21/311 , H01L21/28 , H01L29/423
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US20210083632A1
公开(公告)日：2021-03-18
申请号：US16941691
申请日：2020-07-29
Inventor： Woojin CHANG , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE
Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
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公开(公告)号：US20170236909A1
公开(公告)日：2017-08-17
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun AHN , Dong Min KANG , Yong-Hwan KWON , Dong-Young KIM , SEONG IL KIM , Hae Cheon KIM , Eun Soo NAM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/404 , H01L21/6835 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/401 , H01L29/4175 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L2221/68327 , H01L2221/6834
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US20170133471A1
公开(公告)日：2017-05-11
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min LEE , Byoung-Gue MIN , Hyung Sup YOON , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Ho Kyun AHN , Sang-Heung LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US20140184333A1
公开(公告)日：2014-07-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung LEE , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/30
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a bust packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a bust packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否施加固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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Patent Agency Ranking
公开(公告)号：US20190103483A1
公开(公告)日：2019-04-04
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun AHN , Min Jeong SHIN , Jeong Jin KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Hyung Seok LEE , Jong-Won LIM , Sungjae CHANG , Hyunwook JUNG , Kyu Jun CHO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE , Hong Gu JI
IPC: H01L29/78 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/3065
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US20190081166A1
公开(公告)日：2019-03-14
申请号：US16028612
申请日：2018-07-06
Inventor： Jae Won DO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Byoung-Gue MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jongmin LEE , Jong-Won LIM , Sungjae CHANG , Yoo Jin JANG , Hyunwook JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/205
Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
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公开(公告)号：US20180145684A1
公开(公告)日：2018-05-24
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin CHANG , Jong-Won LIM , Dong Min KANG , Dong-Young KIM , Seong-il KIM , Hae Cheon KIM , Jae Won DO , BYOUNG-GUE MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , JONGMIN LEE , Sungjae CHANG , Yoo Jin JANG , HYUNWOOK JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353
CPC classification number: H03K17/687 , G11C5/14 , H03K3/353 , H03K17/08122 , H03K17/102 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/28 , H03K17/693 , H03K19/0175
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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公开(公告)号：US20170237171A1
公开(公告)日：2017-08-17
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young KIM , Dong Min KANG , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Ho Kyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Yoo Jin JANG , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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公开(公告)号：US20140035044A1
公开(公告)日：2014-02-06
申请号：US14049816
申请日：2013-10-09
Inventor： Hokyun AHN , Jong-Won LIM , Hyung Sup YOON , Byoung-Gue MIN , Sang-Heung LEE , Hae Cheon KIM , Eun Soo NAM
IPC: H01L29/78
CPC classification number: H01L29/7831 , H01L29/2003 , H01L29/404 , H01L29/42316 , H01L29/66462 , H01L29/66863 , H01L29/7787 , H01L29/812
Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.
Abstract translation: 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。
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