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公开(公告)号：US20170236909A1
公开(公告)日：2017-08-17
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun AHN , Dong Min KANG , Yong-Hwan KWON , Dong-Young KIM , SEONG IL KIM , Hae Cheon KIM , Eun Soo NAM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/404 , H01L21/6835 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/401 , H01L29/4175 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L2221/68327 , H01L2221/6834
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US20170133471A1
公开(公告)日：2017-05-11
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min LEE , Byoung-Gue MIN , Hyung Sup YOON , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Ho Kyun AHN , Sang-Heung LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US20230054026A1
公开(公告)日：2023-02-23
申请号：US17891832
申请日：2022-08-19
Inventor： Hyun Wook JUNG , Seong II KIM , Hae Cheon KIM , Youn Sub NOH , Ho Kyun AHN , Sang Heung LEE , Jong Won LIM , Sung Jae CHANG , II Gyu CHOI
IPC: H01L29/778 , H01L29/66 , H01L29/423 , H01L29/40
Abstract: Provided are a nitride-based high electron mobility transistor having enhanced frequency characteristics and an improved structural stability and manufacturing method thereof. The nitride-based high electron mobility transistor includes a first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, source drain electrodes formed on the second semiconductor layer, a first insulating film formed on the second semiconductor layer and having an opening, a dielectric formed on the first insulating film to surround the opening of the first insulating film, a second insulating film formed on an inner sidewall of the dielectric, and a gate electrode formed on the dielectric to fill the opening of the first insulating film and inside the inner sidewall of the dielectric. A width of the inner sidewall at a bottom end of the dielectric is smaller than a width of the inner sidewall at a top end of the dielectric.
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公开(公告)号：US20220285244A1
公开(公告)日：2022-09-08
申请号：US17562587
申请日：2021-12-27
Inventor： Il Gyu CHOI , Seong Il KIM , Hae Cheon KIM , Youn Sub NOH , Ho Kyun AHN , Sang Heung LEE , Jong Won LIM , Sung Jae CHANG , Hyun Wook JUNG
IPC: H01L23/373
Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
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公开(公告)号：US20170237171A1
公开(公告)日：2017-08-17
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young KIM , Dong Min KANG , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Ho Kyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Yoo Jin JANG , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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Patent Agency Ranking
6.发明申请SEMICONDUCTOR DEVICE HAVING STABLE GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权具有稳定的门结构的半导体器件及其制造方法公开(公告)号：US20150236108A1
公开(公告)日：2015-08-20
申请号：US14328247
申请日：2014-07-10
Inventor： Seong Il KIM , Dong Min KANG , Sang Heung LEE , Ho Kyun AHN , Hyung Sup YOON , Byoung Gue MIN , Jong Won LIM
IPC: H01L29/423 , H01L21/283 , H01L29/778
CPC classification number: H01L29/42312 , H01L21/28114 , H01L21/28587 , H01L21/28593 , H01L29/42316 , H01L29/66863 , H01L29/778 , H01L29/812
Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.
Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。
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公开(公告)号：US20150349736A1
公开(公告)日：2015-12-03
申请号：US14666163
申请日：2015-03-23
Inventor： Sang Heung LEE , Dong Min KANG , SEONG IL KIM , Ho Kyun AHN , Hyung Sup YOON , Jong Won LIM , Chull Won JU
CPC classification number: H03G1/0088 , H03F1/083 , H03F3/08 , H03F2200/153 , H03G3/12
Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.
Abstract translation: 本文提供了一种反馈放大器，包括：放大器电路，被配置为放大从输入端输入的输入信号，并将放大的输入信号输出到输出端; 反馈电路，被配置为向输出端子输出的信号施加反馈电阻值，并且通过利用所确定的反馈电阻值施加的偏置电压来调节所述输入信号来控制所述放大器电路的增益; 分组信号传感器，被配置为通过比较来自所述输出端子的输出与最小信号电平之间的比较，产生用于控制所述反馈电阻值中包括的固定电阻值的固定电阻控制信号; 以及固定电阻控制器，其被配置为响应于所述固定电阻控制信号来控制包括在所述反馈电阻值中的所述固定电阻值。
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8.发明申请GaN TRANSISTOR WITH IMPROVED BONDING PAD STRUCTURE AND METHOD OF FABRICATING THE SAME 有权具有改进的粘结片结构的GaN晶体管及其制造方法公开(公告)号：US20150206847A1
公开(公告)日：2015-07-23
申请号：US14453969
申请日：2014-08-07
Inventor： Hae Cheon KIM , Ho Kyun AHN , Byoung Gue MIN , Hyung Sup YOON , Jong Won LIM
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0225 , H01L2224/03466 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/48463 , H01L2924/00014 , H01L2924/10158 , H01L2924/1033 , H01L2924/1304 , H01L2924/13091 , H01L2924/1423 , H01L2924/201 , H01L2924/37001 , H01L2224/45099
Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.
Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。
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公开(公告)号：US20150087142A1
公开(公告)日：2015-03-26
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won LIM , Ho Kyun AHN , Young Rak PARK , Dong Min KANG , Woo Jin CHANG , Seong-il KIM , Sung Bum BAE , Sang-Heung LEE , Hyung Sup YOON , Chull Won JU , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L29/66 , H01L21/311 , H01L21/28 , H01L29/423
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US20140213045A1
公开(公告)日：2014-07-31
申请号：US14230031
申请日：2014-03-31
Inventor： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
IPC: H01L29/66
CPC classification number: H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。
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