公开(公告)号：US5550065A

公开(公告)日：1996-08-27

申请号：US344911

申请日：1994-11-25

申请人： Majid M. Hashemi ,  Saied N. Tehrani ,  Patricia A. Norton

发明人： Majid M. Hashemi ,  Saied N. Tehrani ,  Patricia A. Norton

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47 ,  H01L21/265

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/475 ,  Y10S148/003 ,  Y10S148/10 ,  Y10S148/131 ,  Y10S148/14

摘要： A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

摘要翻译： 制造具有GaAs或InP的半绝缘衬底的自对准FET的方法，其具有通过在邻近表面的衬底中通过分子束外延或金属有机气相外延掺杂表面或外延生长的沟道而形成的导电沟道。 在衬底表面形成高温稳定的LaB6 / TiWN“T型”肖特基栅极接触，用于源极和漏极欧姆区注入到与衬底相邻的衬底中并与“T形”栅极自对准 源极和漏极欧姆触点也相对于栅极自对准。

公开(公告)号：US5514606A

公开(公告)日：1996-05-07

申请号：US270275

申请日：1994-07-05

申请人： Majid M. Hashemi ,  Saied N. Tehrani

发明人： Majid M. Hashemi ,  Saied N. Tehrani

IPC分类号： H01L21/338 ,  H01L23/31 ,  H01L29/812

CPC分类号： H01L29/66863 ,  H01L23/3171 ,  H01L29/812 ,  H01L29/8128 ,  H01L2924/0002 ,  H01L2924/13063

摘要： A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.

摘要翻译： 制造在击穿表面附近的GaAs衬底中形成导电沟道的高耐压MESFET的方法，在衬底的表面上形成高温稳定的源极和漏极欧姆接触和肖特基门接触，并以间隔的关系 ，并在衬底表面和源极，漏极和栅极触点上沉积一层低温GaAs钝化材料。 然后在钝化材料中蚀刻开口以接触源极，漏极和栅极触点。

公开(公告)号：US5640025A

公开(公告)日：1997-06-17

申请号：US566386

申请日：1995-12-01

申请人： Majid M. Hashemi ,  Saied N. Tehrani

发明人： Majid M. Hashemi ,  Saied N. Tehrani

IPC分类号： H01L29/737 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7371

摘要： A high frequency transistor including a heavily doped first current carrying layer positioned on a substrate and a semi-insulating layer of LTGaAs epitaxially grown on the first layer. The semi-insulating layer is etched, using a layer of AlAs as an etch stop, to define an active region and a first current carrying electrode is grown on the exposed first layer in the active region. A control layer is grown on the semi-insulating layer and the first current carrying electrode, and a second current carrying electrode is grown on the control layer. External contacts are formed on the first current carrying layer, the control layer, and the second current carrying electrode.

摘要翻译： 包括位于衬底上的重掺杂的第一载流层和在第一层上外延生长的LTGaAs的半绝缘层的高频晶体管。 使用AlAs层作为蚀刻停止层来蚀刻半绝缘层以限定有源区，并且在有源区中暴露的第一层上生长第一载流电极。 控制层生长在半绝缘层上，第一载流电极和第二载流电极在控制层上生长。 外部触点形成在第一载流层，控制层和第二载流电极上。

公开(公告)号：US5599738A

公开(公告)日：1997-02-04

申请号：US566385

申请日：1995-12-11

申请人： Majid M. Hashemi ,  Saied N. Tehrani ,  Sung P. Pack

发明人： Majid M. Hashemi ,  Saied N. Tehrani ,  Sung P. Pack

IPC分类号： H01L29/872 ,  H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/47 ,  H01L29/812 ,  H01L21/44

CPC分类号： H01L29/66863 ,  H01L21/28132 ,  H01L21/28581 ,  H01L29/42316 ,  H01L29/66462 ,  Y10S438/947

摘要： A process of fabricating submicron features including depositing a gate metal layer on a substrate and forming a first etchable layer of material on the metal layer to define a first sidewall. A second etchable layer is deposited on the structure so as to define a second sidewall. The second etchable layer is etched so as to leave only the second sidewall and the first etchable layer is removed. The metal layer is etched using the second sidewall as an etch mask to form a submicron feature. The width of the feature depends upon the thickness of the metal layer.

摘要翻译： 一种制造亚微米特征的方法，包括在衬底上沉积栅极金属层并在金属层上形成第一可蚀刻材料层以限定第一侧壁。 第二可蚀刻层沉积在结构上以限定第二侧壁。 蚀刻第二可蚀刻层以仅留下第二侧壁，并且去除第一可蚀刻层。 使用第二侧壁作为蚀刻掩模来蚀刻金属层以形成亚微米特征。 特征的宽度取决于金属层的厚度。

公开(公告)号：US06912107B2

公开(公告)日：2005-06-28

申请号：US10830264

申请日：2004-04-21

申请人： Eugene Youjun Chen ,  Mark Durlam ,  Saied N. Tehrani ,  Mark DeHerrera ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

发明人： Eugene Youjun Chen ,  Mark Durlam ,  Saied N. Tehrani ,  Mark DeHerrera ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

IPC分类号： G11B5/39 ,  H01F10/32 ,  H01F41/30 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11B5/127

CPC分类号： B82Y25/00 ,  B82Y40/00 ,  H01F10/324 ,  H01F41/302 ,  H01L43/12 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49052 ,  Y10T428/24917

摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element (10) with insulative veils (34) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

摘要翻译： 一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。 第一电极（14）和第二电极（18）包括铁磁层（26和28）。 间隔层（16）位于第一电极（14）的铁磁层（26）和第二电极（16）的铁磁层（28）之间，用于允许隧道电流沿大致垂直于铁磁层的方向 26和28）。 该装置包括绝缘面纱（34），其特征在于电隔离第一电极（14）和第二电极（18），绝缘面纱（34）包括非磁性和绝缘的介电性质。 另外公开了一种通过氧等离子体灰化技术制造具有绝缘面纱（34）的磁性元件（10）的方法，其已经从具有导电性能转变为绝缘性能。

公开(公告)号：US06835423B2

公开(公告)日：2004-12-28

申请号：US10349702

申请日：2003-01-22

申请人： Eugene Youjun Chen ,  Mark Durlam ,  Saied N. Tehrani ,  Mark DeHerrera ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

发明人： Eugene Youjun Chen ,  Mark Durlam ,  Saied N. Tehrani ,  Mark DeHerrera ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

IPC分类号： H05H100

CPC分类号： B82Y25/00 ,  B82Y40/00 ,  H01F10/324 ,  H01F41/302 ,  H01L43/12 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49052 ,  Y10T428/24917

摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element (10) with insulative veils (34) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

摘要翻译： 一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。 第一电极（14）和第二电极（18）包括铁磁层（26和28）。 间隔层（16）位于第一电极（14）的铁磁层（26）和第二电极（16）的铁磁层（28）之间，用于允许隧道电流沿大致垂直于铁磁层的方向 26和28）。 该装置包括绝缘面纱（34），其特征在于电隔离第一电极（14）和第二电极（18），绝缘面纱（34）包括非磁性和绝缘的介电性质。 另外公开了一种通过氧等离子体灰化技术制造具有绝缘面纱（34）的磁性元件（10）的方法，其已经从具有导电性能转变为绝缘性能。

公开(公告)号：US06512689B1

公开(公告)日：2003-01-28

申请号：US10051646

申请日：2002-01-18

申请人： Peter K. Naji ,  Mark A. Durlam ,  Saied N. Tehrani

发明人： Peter K. Naji ,  Mark A. Durlam ,  Saied N. Tehrani

IPC分类号： G11C1100

CPC分类号： G11C7/14 ,  G11C11/15

摘要： A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.

摘要翻译： 没有隔离装置的磁阻随机存取存储器架构包括多个非易失性磁阻元件的数据列。 参考柱包括与数据列相邻定位的非易失性磁阻元件。 每列连接到当前输送机。 选择的数据流传输器和参考电流传输器连接到差分放大器的输入端，用于将数据电压与参考电压进行差分比较。 目前的输送机直接连接到数据和参考位线的末端。 这种特定的布置允许当前输送机被夹紧到相同的电压，这减少或去除潜行电路以显着减少泄漏电流。

公开(公告)号：US5959880A

公开(公告)日：1999-09-28

申请号：US993996

申请日：1997-12-18

申请人： Jing Shi ,  Theodore Zhu ,  Saied N. Tehrani ,  Eugene Chen ,  Mark Durlam

发明人： Jing Shi ,  Theodore Zhu ,  Saied N. Tehrani ,  Eugene Chen ,  Mark Durlam

IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/56 ,  G11C11/00

CPC分类号： G11C11/5607 ,  G11C11/15 ,  G11C11/16 ,  G11C2211/5615

摘要： A low aspect ratio magnetoresistive tunneling junction memory cell includes two layers of magnetoresistive material separated by electrically insulating material so as to form a magnetoresistive tunneling junction. An exchange interaction layer is sandwiched between one layer of the junction and a third layer of magnetoresistive material so as to pin the magnetic vector of one layer of the junction anti-parallel to a magnetic vector in the third layer so that magnetostatic interaction between the junction layers is canceled and the magnetic vector of the one layer is free to move in either of the two directions parallel to the polarization axis. Antiferromagnetic material is positioned adjacent the third layer so as to fix the magnetic vector in the third layer uni-directionally parallel to the polarization axis.

摘要翻译： 低纵横比磁阻隧穿结存储单元包括由电绝缘材料分开的两层磁阻材料，以形成磁阻隧道结。 交换相互作用层夹在一层结和第三层磁阻材料之间，以便将一层结的磁矢量与第三层中的磁矢量平行地平行，从而使连接点之间的静磁相互作用 层被取消，并且一层的磁矢量在平行于偏振轴的两个方向中的任一方向上自由移动。 反铁磁材料位于第三层附近，以将磁矢量固定在与偏振轴方向平行的第三层中。

公开(公告)号：US5902690A

公开(公告)日：1999-05-11

申请号：US806275

申请日：1997-02-25

申请人： Clarence J. Tracy ,  Eugene Chen ,  Mark Durlam ,  Theodore Zhu ,  Saied N. Tehrani

发明人： Clarence J. Tracy ,  Eugene Chen ,  Mark Durlam ,  Theodore Zhu ,  Saied N. Tehrani

IPC分类号： G11C11/15 ,  H01L27/22 ,  B32B9/00

CPC分类号： H01L27/228 ,  G11C11/15 ,  Y10S977/838 ,  Y10T428/1164

摘要： A non-volatile magneto-resistive memory positioned on a semiconductor substrate is shielded from stray magnetic fields by a passivation layer partially or completely surrounding the non-volatile magneto-resistive memory. The passivation layer includes non-conductive ferrite materials, such as Mn--Zn-Ferrite, Ni--Zn-Ferrite, MnFeO, CuFeO, FeO, or NiFeO, for shielding the non-volatile magneto-resistive memory from stray magnetic fields. The non-conductive ferrite materials may also be in the form of a layer which focuses internally generated magnetic fields on the non-volatile magneto-resistive memory to reduce power requirements.

摘要翻译： 定位在半导体衬底上的非易失性磁阻存储器通过部分或完全围绕非易失性磁阻存储器的钝化层与杂散磁场屏蔽。 钝化层包括非导电铁氧体材料，例如Mn-Zn-铁素体，Ni-Zn-铁素体，MnFeO，CuFeO，FeO或NiFeO，用于屏蔽非易失性磁阻存储器与杂散磁场。 非导电铁氧体材料也可以是将内部产生的磁场聚焦在非易失性磁阻存储器上以降低功率需求的层的形式。

公开(公告)号：US5804458A

公开(公告)日：1998-09-08

申请号：US766076

申请日：1996-12-16

申请人： Saied N. Tehrani ,  Mark Durlam ,  Herbert Goronkin

发明人： Saied N. Tehrani ,  Mark Durlam ,  Herbert Goronkin

IPC分类号： H01L27/115 ,  H01L21/70

CPC分类号： H01L27/115 ,  H01L27/222 ,  H01L43/12

摘要： A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.

摘要翻译： 公开了一种制造多个间隔开的亚微米存储器单元的方法，包括以下步骤：在衬底形成上沉积磁阻系统，沉积和图形化第一材料层以形成侧壁，以及沉积第二层可选择的可蚀刻的 材料在第一层材料上蚀刻第二层材料以在第一材料层的侧壁上限定间隔物，使用间隔物作为掩模蚀刻磁阻系统以限定多个间隔开的亚微米磁存储器单元 并且在多个间隔开的亚微米磁存储器单元上沉积电触点。