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129 条记录 (耗时 0.028 秒)

    LDMOS with improved breakdown voltage
    3.
    发明授权
    LDMOS with improved breakdown voltage 有权
    LDMOS具有改善的击穿电压

    公开(公告)号：US08748271B2

    公开(公告)日：2014-06-10

    申请号：US13046313

    申请日：2011-03-11

    申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    IPC分类号： H01L29/772 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423

    CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

    摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

    Novel methods to reduce gate contact resistance for AC reff reduction
    5.
    发明申请
    Novel methods to reduce gate contact resistance for AC reff reduction 有权
    降低栅极接触电阻的新方法

    公开(公告)号：US20120038009A1

    公开(公告)日：2012-02-16

    申请号：US12806354

    申请日：2010-08-11

    申请人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    发明人： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

    摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

    摘要翻译： 制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。 执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。 这导致较低的栅极接触电阻并有效降低器件的AC Reff。

    Semiconductor device with reduced contact resistance and method of manufacturing thereof
    6.
    发明申请
    Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
    具有降低的接触电阻的半导体器件及其制造方法

    公开(公告)号：US20120018815A1

    公开(公告)日：2012-01-26

    申请号：US12804487

    申请日：2010-07-22

    申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

    发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

    摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

    摘要翻译： 制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。 这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE
    8.
    发明申请
    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
    LDMOS具有改进的断电电压

    公开(公告)号：US20120228705A1

    公开(公告)日：2012-09-13

    申请号：US13046332

    申请日：2011-03-11

    申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

    摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE
    9.
    发明申请
    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
    LDMOS具有改进的断电电压

    公开(公告)号：US20120228695A1

    公开(公告)日：2012-09-13

    申请号：US13046313

    申请日：2011-03-11

    申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

    摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

    LDMOS with two gate stacks having different work functions for improved breakdown voltage
    10.
    发明授权
    LDMOS with two gate stacks having different work functions for improved breakdown voltage 有权
    LDMOS具有两个栅极叠层，具有不同的功能，可提高击穿电压

    公开(公告)号：US09034711B2

    公开(公告)日：2015-05-19

    申请号：US13046332

    申请日：2011-03-11

    申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

    CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

    摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。