公开(公告)号：US20110271141A1

公开(公告)日：2011-11-03

申请号：US12771293

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G06F11/008 ,  G06F11/0724 ,  G06F11/0787 ,  G06F11/0793

摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.

摘要翻译： 提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。 耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。 片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。 片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。 即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。 片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

公开(公告)号：US08386859B2

公开(公告)日：2013-02-26

申请号：US12771387

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G11C29/00 ,  G11C7/00 ,  G01R31/28 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G06F11/00

CPC分类号： G06F11/3062 ,  G06F11/24 ,  G06F11/3024 ,  G06F11/3089

摘要： Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.

摘要翻译： 提供了用于控制集成电路芯片上的一个或多个芯的操作的机构。 该机制从集成电路芯片的片上非易失性存储器中检索表示集成电路芯片在数据处理系统中操作之前的一个或多个核的操作特性的基准芯片特性数据。 将一个或多个核的当前操作特征数据与基线芯片特性数据进行比较。 确定当前操作特性数据与基线芯片特性数据的偏差并用于确定对一个或多个芯的操作的修改。 基于所确定的修改，控制信号被发送到一个或多个片上管理单元，以使得修改一个或多个核的操作。

公开(公告)号：US08276018B2

公开(公告)日：2012-09-25

申请号：US12771293

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G06F11/00

CPC分类号： G06F11/008 ,  G06F11/0724 ,  G06F11/0787 ,  G06F11/0793

摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.

摘要翻译： 提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。 耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。 片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。 片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。 即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。 片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

公开(公告)号：US20110271161A1

公开(公告)日：2011-11-03

申请号：US12771387

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G06F11/07

CPC分类号： G06F11/3062 ,  G06F11/24 ,  G06F11/3024 ,  G06F11/3089

摘要： Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.

摘要翻译： 提供了用于控制集成电路芯片上的一个或多个芯的操作的机构。 该机制从集成电路芯片的片上非易失性存储器中检索表示集成电路芯片在数据处理系统中操作之前的一个或多个核的操作特性的基准芯片特性数据。 将一个或多个核的当前操作特征数据与基线芯片特性数据进行比较。 确定当前操作特性数据与基线芯片特性数据的偏差并用于确定对一个或多个芯的操作的修改。 基于所确定的修改，控制信号被发送到一个或多个片上管理单元，以使得修改一个或多个核的操作。

公开(公告)号：US08141020B2

公开(公告)日：2012-03-20

申请号：US12493599

申请日：2009-06-29

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.

摘要翻译： 在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。 对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。 如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。 对于每个含设备的层中的所有相邻的功能块对，重复此例程。 随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。 该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

公开(公告)号：US20110286190A1

公开(公告)日：2011-11-24

申请号：US12774223

申请日：2010-05-20

申请人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

发明人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

IPC分类号： H05K7/02

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。 该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。 主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成 元件具有相对于主体层和芯片的平滑表面。

公开(公告)号：US08677613B2

公开(公告)日：2014-03-25

申请号：US12774223

申请日：2010-05-20

申请人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

发明人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

IPC分类号： H05K3/30

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。 该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。 主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成 元件具有相对于主体层和芯片的平滑表面。

公开(公告)号：US20120268909A1

公开(公告)日：2012-10-25

申请号：US13535660

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： H05K7/02

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 一种三维计算机处理芯片堆叠，其包括布置在堆叠中的至少一个其他层上的主机层。 主体层包括形成在其上的空腔，用于接收预先配置有相对于彼此的异质特性的芯片。 形成空腔以适应芯片的不均匀性质。 芯片被连接到空腔的相应表面，从而形成相对于主体层和芯片具有平滑表面的元件。

公开(公告)号：US09390989B2

公开(公告)日：2016-07-12

申请号：US13535694

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50 ,  H01L23/14 ,  H05K3/46 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H01L21/48

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.

摘要翻译： 一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的计算机程序产品。 计算机可读程序代码包括被配置为从多个客户端接收系统需求的计算机可读程序代码，从系统要求中识别公共处理结构和技术，以及将公共处理结构和技术分配给3D计算机处理中的至少一个层 芯片堆栈计划。 计算机可读程序代码还被配置用于根据系统要求识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。 计算机可读程序代码还被配置用于确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。 制造设备构成3D计算机处理芯片堆栈。

公开(公告)号：US09798654B2

公开(公告)日：2017-10-24

申请号：US13233714

申请日：2011-09-15

申请人： Philip G. Emma ,  Eren Kursun

发明人： Philip G. Emma ,  Eren Kursun

IPC分类号： G06F12/02 ,  G11C13/00 ,  G11C7/04

CPC分类号： G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/2024 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069

摘要： Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.