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9 条记录 (耗时 0.021 秒)

    Register renaming to reduce bypass and increase apparent physical register size
    1.
    发明授权
    Register renaming to reduce bypass and increase apparent physical register size 失效
    注册重命名以减少旁路并增加明显的物理寄存器大小

    公开(公告)号：US06944751B2

    公开(公告)日：2005-09-13

    申请号：US10074098

    申请日：2002-02-11

    申请人： Eric S. Fetzer ,  Donald C. Soltis, Jr. ,  Stephen R. Undy

    发明人： Eric S. Fetzer ,  Donald C. Soltis, Jr. ,  Stephen R. Undy

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/312

    CPC分类号： G06F9/3855 ,  G06F9/30123 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3842

    摘要： The invention provides a processor architecture that bypasses data hazards. The architecture has an array of pipelines and a register file. Each of the pipelines includes an array of execution units. The register file has a first section of n registers (e.g., 128 registers) and a second section of m registers (e.g., 16 registers). A write mux couples speculative data from the execution units to the second set of m registers and non-speculative data from a write-back stage of the execution units to the first section of n registers. A read mux couples the speculative data from the second set of m registers to the execution units to bypass data hazards within the execution units. The register file preferably includes column decode logic for each of the registers in the second section of m registers to architect speculative data without moving data. The decode logic first decodes, and then selects, an age of the producer of the speculative state; the newest producer enables the decode.

    摘要翻译： 本发明提供了绕过数据危害的处理器架构。 该架构具有一系列管道和一个寄存器文件。 每个管道都包括执行单元的数组。 寄存器文件具有n个寄存器（例如，128个寄存器）的第一部分和m个寄存器的第二部分（例如，16个寄存器）。 写入多路复用器将来自执行单元的推测数据从执行单元的写回阶段到n个寄存器的第一部分将来自执行单元的推测数据耦合到第二组m个寄存器和非推测数据。 读取多路复用器将来自第二组m个寄存器的推测数据耦合到执行单元以绕过执行单元内的数据危险。 寄存器文件优选地包括用于m个寄存器的第二部分中的每个寄存器的列解码逻辑，以构建不移动数据的推测数据。 解码逻辑首先解码，然后选择投机状态的生产者的年龄; 最新的制作商可以进行解码。

    System and method for measuring current
    3.
    发明授权
    System and method for measuring current 失效
    用于测量电流的系统和方法

    公开(公告)号：US07123104B2

    公开(公告)日：2006-10-17

    申请号：US10644542

    申请日：2003-08-20

    申请人： Christopher J. Bostak ,  Samuel D. Naffziger ,  Christopher A. Poirier ,  Eric S. Fetzer

    发明人： Christopher J. Bostak ,  Samuel D. Naffziger ,  Christopher A. Poirier ,  Eric S. Fetzer

    IPC分类号： H03B5/24 ,  G01R19/00 ,  H03K17/296

    CPC分类号： G01R19/252 ,  G01R19/0092

    摘要： The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

    摘要翻译： 本发明涉及一种用于测量集成电路中的电流的系统和方法，包括使用第一测量电压测量来自第一压控振荡器（VCO）的第一输出计数，同时使用第二测量电压测量来自第二VCO的第二输出计数 第二测量电压，并且使用与第一和第二输出计数之间的差成比例的电压来计算集成电路中的电流。

    Receiver and method for mitigating temporary logic transitions
    5.
    发明授权
    Receiver and method for mitigating temporary logic transitions 有权
    用于缓解临时逻辑转换的接收器和方法

    公开(公告)号：US07200821B2

    公开(公告)日：2007-04-03

    申请号：US11089576

    申请日：2004-06-07

    申请人： Lei Wang ,  Eric S. Fetzer

    发明人： Lei Wang ,  Eric S. Fetzer

    IPC分类号： G06F17/50

    CPC分类号： H04L25/0292 ,  G06F17/5045 ,  H03K19/00361

    摘要： A circuit and method for receiving data signals over a data signal line are disclosed. In one embodiment, a receiver circuit is provided for receiving data signals transmitted over a signal line. The receiver circuit comprises an inverter circuit having an input that forms an input of the receiver circuit and an output coupled to an internal node, an output circuit having an input coupled to the internal node and an output that provides an output of the receiver circuit, and a charge adding circuit that provides at least a portion of a temporary logic transition at the input of the receiver circuit, induced by a logic transition on an adjacent signal line, to the internal node to mitigate erroneous logic transitions associated with the receiver circuit.

    摘要翻译： 公开了一种通过数据信号线接收数据信号的电路和方法。 在一个实施例中，提供接收器电路用于接收通过信号线传输的数据信号。 接收机电路包括一个反相器电路，该反相器电路具有形成接收器电路的输入和耦合到内部节点的输出的输入端，具有耦合到内部节点的输入的输出电路和提供接收器电路的输出的输出， 以及充电添加电路，其将由接收器电路的输入端引起的临时逻辑转换的至少一部分提供给内部节点，以缓解与接收器电路相关联的错误逻辑转换。

    System to temporarily modify an output waveform
    6.
    发明授权
    System to temporarily modify an output waveform 失效
    系统暂时修改输出波形

    公开(公告)号：US07199611B2

    公开(公告)日：2007-04-03

    申请号：US10646936

    申请日：2003-08-22

    申请人： Samuel D. Naffziger ,  Eric S. Fetzer

    发明人： Samuel D. Naffziger ,  Eric S. Fetzer

    IPC分类号： H01L7/085

    CPC分类号： H03K5/06 ,  G01R31/2856 ,  G01R31/31928 ,  H03K19/018585

    摘要： Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

    摘要翻译： 公开了用于提供临时修改的输出的系统和方法。 波形控制提供在第一操作模式期间临时调整到正常高电平和低电平之间的中间电平的控制输出。 波形控制提供控制输出以在第二操作模式期间在高电平和低电平之间周期性地跳变。 延迟网络控制波形控制，以在第一操作模式期间的中间级提供输出持续一段时间。

    Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority
    7.
    发明授权
    Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority 失效
    多分配CPU集成电路具有虚拟化和模块化资源，可调整调度优先级

    公开(公告)号：US06895497B2

    公开(公告)日：2005-05-17

    申请号：US10092714

    申请日：2002-03-06

    申请人： Eric S. Fetzer ,  Wayne Kever ,  Eric DeLano

    发明人： Eric S. Fetzer ,  Wayne Kever ,  Eric DeLano

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3851

    摘要： A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

    摘要翻译： 多调度处理器具有多个指令获取单元，每个指令提取单元用于向指令解码和调度单元提供指令流。 处理器还具有资源分配单元，以及多个资源，例如组合的整数和地址执行管线和浮点执行管线。 每个指令解码和调度单元请求执行资源分配单元的指令所需的资源，该指令在多个指令解码和调度单元之间进行仲裁。

    Method and circuit for measuring on-chip, cycle-to-cycle clock jitter
    8.
    发明授权
    Method and circuit for measuring on-chip, cycle-to-cycle clock jitter 失效
    用于测量片上，周期到周期时钟抖动的方法和电路

    公开(公告)号：US06841985B1

    公开(公告)日：2005-01-11

    申请号：US10630175

    申请日：2003-07-29

    申请人： Eric S. Fetzer

    发明人： Eric S. Fetzer

    IPC分类号： G01R25/00 ,  G01R31/317 ,  G01R23/12

    CPC分类号： G01R31/31709 ,  G01R25/005 ,  G01R31/31725

    摘要： The invention provides a method and circuit for measuring on-chip, cycle-to-cycle, jitter. Copies of a circuit comprising a programmable delay line, a programmable phase comparator, and two counters are placed at different locations on an IC near a clock signal. The programmable delay line creates a clock signal that is delayed by one clock cycle. This delayed clock signal is compared in time to the original clock signal by the programmable phase comparator. If the difference in time between the delayed clock signal and the clock signal is greater than the dead time, the first counter is triggered. If the difference in time is negative and the absolute value is greater than the dead time, the second counter is triggered. A statistical distribution, based on the values of the counters, is created. This distribution is used to predict on-chip, cycle-to-cycle jitter.

    摘要翻译： 本发明提供一种用于测量片上，周期到周期，抖动的方法和电路。 包括可编程延迟线，可编程相位比较器和两个计数器的电路的副本被放置在靠近时钟信号的IC上的不同位置处。 可编程延迟线产生延迟一个时钟周期的时钟信号。 该延迟时钟信号在可编程相位比较器上与原始时钟信号在时间上进行比较。 如果延迟时钟信号和时钟信号之间的时间差大于死区时间，则触发第一个计数器。 如果时间差为负，绝对值大于死区时间，则触发第二个计数器。 创建基于计数器值的统计分布。 该分布用于预测片上，周期到周期的抖动。

    Adapting VLSI clocking to short term voltage transients
    9.
    发明授权
    Adapting VLSI clocking to short term voltage transients 有权
    适应VLSI时钟短期电压瞬变

    公开(公告)号：US06586971B1

    公开(公告)日：2003-07-01

    申请号：US10020114

    申请日：2001-12-18

    申请人： Samuel Naffziger ,  Eric S. Fetzer

    发明人： Samuel Naffziger ,  Eric S. Fetzer

    IPC分类号： H03D1300

    CPC分类号： G06F1/10 ,  G06F1/305

    摘要： A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.

    摘要翻译： 一种补偿集成电路中电压下降的系统和方法。 集成电路可以包括多个芯片电路，时钟控制系统，包括至少一个延迟元件和电压下降检测器的时钟分配网络。 当检测到电压下降时，时钟控制系统通过使用至少一个延迟元件来适应时钟分配网络中的周期时间。 该方法可以包括检测集成电路中的电压下降，其中集成电路由时钟信号驱动，确定最佳频率变化以补偿电压下降，并以递增方式调整时钟信号的周期时间以实现 最佳频率变化。