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    Immersion scanning system for fabricating porous silicon films
    1.
    发明授权
    Immersion scanning system for fabricating porous silicon films 失效
    用于制造多孔硅膜的浸渍扫描系统

    公开(公告)号：US5501787A

    公开(公告)日：1996-03-26

    申请号：US395936

    申请日：1995-02-27

    申请人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Vijay P. Kesan

    发明人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Vijay P. Kesan

    IPC分类号： H01L21/3063 ,  H01L21/306 ,  H01L33/00 ,  H01L33/34 ,  C25D7/12 ,  C25D11/32

    CPC分类号： H01L33/346 ,  H01L21/306 ,  H01L33/0054

    摘要： A system for making porous silicon on blank and patterned Si substrates by "immersion scanning", particularly suitable for fabricating light-emitting Si devices and utilizing an open electrolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation. The light-emitting silicon devices produced incorporate porous silicon layers and are operable at room temperature.

    摘要翻译： 一种用于通过“浸没扫描”在空白和图案化的Si衬底上制造多孔硅的系统，特别适用于制造发光的Si器件，并利用具有由Si衬底组成的阴极和相对阳极的开放电解池，多孔硅 将被形成为两者彼此相对的平面布置在包含在电池中的HF水溶液电解液中。 基板阳极安装成相对于电解质可移动，以便在阳极氧化期间以可编程的速率机械地循环或扫描电解质中和从电解液中扫出。 基板上得到的阳极氧化层的均匀度，厚度和孔隙率由系统的扫描速度，循环次数，电流密度和HF基电解质参数以及Si衬底电阻率，导电类型和晶体取向 。 所制造的发光硅器件包括多孔硅层，并且可在室温下操作。

    High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields
    2.
    发明授权
    High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields 失效
    具有凹陷电极和厚氧化物的高速硅基侧面光电探测器，以减少边缘场

    公开(公告)号：US5525828A

    公开(公告)日：1996-06-11

    申请号：US294897

    申请日：1994-08-23

    申请人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Rajiv V. Joshi ,  Vijay P. Kesan ,  Michael R. Scheuermann ,  Massimo A. Ghioni

    发明人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Rajiv V. Joshi ,  Vijay P. Kesan ,  Michael R. Scheuermann ,  Massimo A. Ghioni

    IPC分类号： H01L31/02 ,  H01L31/105 ,  H01L31/108 ,  H01L31/07

    CPC分类号： H01L31/105 ,  H01L31/02024 ,  H01L31/1085

    摘要： Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology. A further feature involves isolating the semiconductor surface layer from the substrate by a layer that may be either 1) transparent and insulating, 2) optically absorbing, or 3) optically reflecting, so that the photocarriers recombine before they can be collected by the field. In the latter case, the photodetector acts as a resonant cavity, resulting in an increase in the number of carriers that are generated, and hence a more sensitive device.

    摘要翻译： 在硅表面上公开了金属 - 半导体 - 金属光电探测器（MSM-PD）或横向p-i-n光电检测器（LPIN-PD）形式的硅 - VLSI兼容光电探测器。 MSM-PD的电极具有对于硅的中等到高电子和空穴阻挡高度，用于形成肖特基势垒，并且通过使用自对准金属化制造成凹入硅的表面半导体层 通过选择性沉积或通过选择性反应和蚀刻，以类似于SALICIDE概念的方式。 通过用透明氧化膜涂覆衬底的暴露的Si表面开始制造，使得Si /氧化物界面表现出低的表面复合速度。 然后通过光刻法将交错图案通过氧化膜蚀刻以暴露Si表面，并且使用自对准金属化选择性地在暴露的Si表面中形成金属电极构件，以产生凹陷在硅表面下方的薄的叉指电极，其本身可以是 在较薄的Si层上。 这些电极可以间隔开，以最小化叉指运送通过时间并使灵敏度最大化，并且整个过程和结构与传统的硅集成电路（IC）技术相兼容。 另一个特征包括通过可以是1）透明和绝缘，2）光学吸收或3）光学反射的层将衬底的半导体表面层隔离，使得光载流子在它们可以被场收集之前复合。 在后一种情况下，光电探测器用作谐振腔，导致所产生的载流子数量增加，因此增加了更敏感的装置。

    Apparatus for producing porous silicon on a substrate
    3.
    发明授权
    Apparatus for producing porous silicon on a substrate 失效
    用于在基板上制造多孔硅的装置

    公开(公告)号：US5458756A

    公开(公告)日：1995-10-17

    申请号：US266444

    申请日：1994-06-27

    申请人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Vijay P. Kesan

    发明人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Vijay P. Kesan

    IPC分类号： H01L21/3063 ,  H01L21/306 ,  H01L33/00 ,  H01L33/34 ,  C25D17/00 ,  C25F7/00

    CPC分类号： H01L33/346 ,  H01L21/306 ,  H01L33/0054

    摘要： A system for making porous silicon on blank and patterned Si substrates by "immersion scanning", particularly suitable for fabricating light-emitting Si devices and utilizing an open electolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation. The light-emitting silicon devices produced incorporate porous silicon layers and are operable at room temperature.

    摘要翻译： 一种用于通过“浸没扫描”在空白和图案化的Si衬底上制造多孔硅的系统，特别适用于制造发光的Si器件，并且利用具有阴极和由Si衬底组成的相对阳极的开放电解槽，多孔硅 将被形成为两者彼此相对的平面布置在包含在电池中的HF水溶液电解液中。 基板阳极安装成相对于电解质可移动，以便在阳极氧化期间以可编程的速率机械地循环或扫描电解质中和从电解液中扫出。 基板上得到的阳极氧化层的均匀度，厚度和孔隙率由系统的扫描速度，循环次数，电流密度和HF基电解质参数以及Si衬底电阻率，导电类型和晶体取向 。 所制造的发光硅器件包括多孔硅层，并且可在室温下操作。

    Charge electrode array and combination for ink jet printing and method of manufacture
    5.
    发明授权
    Charge electrode array and combination for ink jet printing and method of manufacture 失效
    用于喷墨印刷的电荷电极阵列和组合以及制造方法

    公开(公告)号：US4047184A

    公开(公告)日：1977-09-06

    申请号：US653168

    申请日：1976-01-28

    申请人： Ernest Bassous ,  Lawrence Kuhn

    发明人： Ernest Bassous ,  Lawrence Kuhn

    IPC分类号： B41J2/16 ,  B41J2/085 ,  B41J2/09 ,  G01D15/18 ,  G06K15/10 ,  H04N1/034

    CPC分类号： G01D15/18 ,  B41J2/085

    摘要： A charge electrode array for use in an ink jet printing apparatus is formed by anisotropic etching of apertures through a single crystal silicon substrate of (110) orientation. Conductive diffusion layers in the walls of and adjacent to the apertures permit a charge to be placed on a jet stream passing through the apertures. Contacts can be formed on the adjacent diffusion layers to provide connection to an externally located charging circuit or the contacts may be omitted when the charging circuit is formed in the substrate itself and connected by diffusion or a metal layer to each adjacent diffusion layer. Jet nozzles and synchronization electrodes are shown incorporated in the charge electrode array to form a monolithic structure capable of performing a plurality of functions. Substrate contacts are also provided for biasing.

    摘要翻译： 用于喷墨打印设备的充电电极阵列通过各向异性蚀刻通过（110）取向的单晶硅衬底的孔而形成。 导电扩散层在孔的壁中并且邻近孔允许电荷被放置在穿过孔的喷射流上。 可以在相邻扩散层上形成接触以提供与外部位于的充电电路的连接，或者当充电电路形成在衬底本身中并且通过扩散或金属层连接到每个相邻的扩散层时，可以省略触点。 喷射喷嘴和同步电极显示为并入电荷电极阵列中以形成能够执行多种功能的单片结构。 还提供衬底触点用于偏置。

    Method for fabricating transistor structures having very short effective channels
    8.
    发明授权
    Method for fabricating transistor structures having very short effective channels 失效
    制造具有非常短的有效通道的晶体管结构的方法

    公开(公告)号：US4173818A

    公开(公告)日：1979-11-13

    申请号：US910254

    申请日：1978-05-30

    申请人： Ernest Bassous ,  Tak H. Ning ,  Carlton M. Osburn

    发明人： Ernest Bassous ,  Tak H. Ning ,  Carlton M. Osburn

    IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  B01J17/00

    CPC分类号： H01L29/7816 ,  H01L21/033 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7835

    摘要： A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.

    摘要翻译： 一种包括一系列工艺步骤的方法，用于制造具有非常短的有效通道长度的绝缘栅场效应晶体管。 在该方法的第一版本中，器件的源极和漏极区域在一个处理步骤中被打开，并且在一个掩模步骤中实现源极和漏极到栅极的自对准。 然后对漏极区进行掩模，并且注入沟道的源极侧以调整高阈值电压沟道区的阈值电压。 在该方法的第二版本中，源极区域在漏极区域打开之前被打开并与栅极自对准。 在漏极区域打开之前进行用于调整高阈值电压沟道区域的阈值电压的植入，然后在另外的掩模步骤中，漏极区域被打开并与栅极自对准。 在任一版本中，阈值电压是可调节的，并且通道长度被控制为小的值。

    Epitaxial silicon membranes
    9.
    发明授权
    Epitaxial silicon membranes 失效
    外延硅膜

    公开(公告)号：US5357899A

    公开(公告)日：1994-10-25

    申请号：US120290

    申请日：1993-09-13

    申请人： Ernest Bassous ,  Bernard S. Meyerson ,  Kevin J. Uram

    发明人： Ernest Bassous ,  Bernard S. Meyerson ,  Kevin J. Uram

    IPC分类号： G01L9/00 ,  G03F1/22 ,  H01L21/027 ,  H01L21/20 ,  H01L21/205 ,  H01L21/306 ,  C30B1/08

    CPC分类号： G03F1/22 ,  G01L9/0042 ,  H01L21/30608

    摘要： The subject invention provides a silicon membrane material made from silicon that is epitaxially deposited at low temperatures greater than or equal to 500.degree. C. and doped with controlled amounts of boron and germanium. A silicon membrane structure is provided and made by one or more layers of ultra thin epitaxially deposited silicon layers that are precisely controlled in both thickness and composition. At least one of the layers is doped with boron in a concentration range greater than 2.times.10.sup.20 atoms of boron per cubic centimeter of silicon, or with germanium in a concentration range greater than 5.times.10.sup.20 atoms of germanium per cubic centimeter of silicon, or with a combination of boron and germanium in these concentration ranges. A silicon membrane fabrication process is also provided which requires no additional masking film to protect the membrane surface during KOH etching of the bulk silicon substrate.

    摘要翻译： 本发明提供了由硅制成的硅膜材料，其在大于或等于500℃的低温下外延沉积，并掺杂受控量的硼和锗。 硅膜结构由一层或多层超薄外延沉积的硅层提供并制成，其在厚度和组成上精确控制。 这些层中的至少一层掺杂了硼，其浓度范围大于每立方厘米硅的2×1020个原子的硼，或者锗浓度范围大于每立方厘米硅的5×1020原子，或者与 硼和锗在这些浓度范围内。 还提供了硅膜制造方法，其不需要额外的掩模膜来在体硅衬底的KOH蚀刻期间保护膜表面。