公开(公告)号：US20080093664A1

公开(公告)日：2008-04-24

申请号：US11894449

申请日：2007-08-21

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Dong-Won Kim ,  Sung-Hwan Kim

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Dong-Won Kim ,  Sung-Hwan Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10876 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7926

摘要： In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending between the first gate electrode and the second gate electrode. The first gate electrode is used for removing a charge trapped in the second gate insulating layer. Thus, the memory device can have an improved characteristic when performing an erase operation.

摘要翻译： 在存储器件和存储器件的制造方法中，存储器件包括由第一栅极绝缘层包围的第一栅极电极，由可以是ONO层的第二栅极绝缘层包围的第二栅电极，以及通道 在第一栅电极和第二栅电极之间垂直延伸的区域。 第一栅电极用于去除在第二栅极绝缘层中俘获的电荷。 因此，当执行擦除操作时，存储器件可以具有改进的特性。

公开(公告)号：US07790494B2

公开(公告)日：2010-09-07

申请号：US12007819

申请日：2008-01-16

申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

IPC分类号： H01L21/00 ,  H01L35/24 ,  H01L51/00 ,  H01L29/792

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

公开(公告)号：US20080185668A1

公开(公告)日：2008-08-07

申请号：US12007819

申请日：2008-01-16

申请人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

发明人： Min-Sang Kim ,  Sung-Young Lee ,  Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim ,  Dong-Gun Park

IPC分类号： H01L29/84 ,  H01L21/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673

摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

摘要翻译： 存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。 位线可以在第一方向上形成在基板上。 第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。 焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。 第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。 第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

公开(公告)号：US20080094895A1

公开(公告)日：2008-04-24

申请号：US11803425

申请日：2007-05-15

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

IPC分类号： G11C11/34 ,  H01L21/44

CPC分类号： H01L27/101 ,  H01L27/24

摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.

摘要翻译： 非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。 在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线 字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开 从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

公开(公告)号：US07768070B2

公开(公告)日：2010-08-03

申请号：US11832589

申请日：2007-08-01

申请人： Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

发明人： Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

摘要翻译： 一种具有场效应晶体管的半导体器件及其制造方法。 通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。 原位掺杂的外延图案贯穿整个杂质浓度。 因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。 结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

公开(公告)号：US07723762B2

公开(公告)日：2010-05-25

申请号：US11598374

申请日：2006-11-13

申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim

发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Dong-Won Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78618 ,  H01L29/78684

摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.

摘要翻译： 提供肖特基势垒FinFET器件及其制造方法。 该装置包括设置在基板上的下部翅片体。 提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。 提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。 肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层 并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

公开(公告)号：US20050158934A1

公开(公告)日：2005-07-21

申请号：US11030770

申请日：2005-01-05

申请人： Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

发明人： Eun-Jung Yun ,  Hye-Jin Cho ,  Dong-Won Kim ,  Sung-Min Kim

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L21/425

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

摘要翻译： 一种具有场效应晶体管的半导体器件及其制造方法。 通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。 原位掺杂的外延图案贯穿整个杂质浓度。 因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。 结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

公开(公告)号：US07511998B2

公开(公告)日：2009-03-31

申请号：US11803425

申请日：2007-05-15

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

IPC分类号： G11C16/04

CPC分类号： H01L27/101 ,  H01L27/24

摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.

摘要翻译： 非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。 在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线 字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开 从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

公开(公告)号：US07719068B2

公开(公告)日：2010-05-18

申请号：US12002668

申请日：2007-12-18

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： G11C11/50

CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

摘要： There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件和制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线 并且沿第一方向延伸; 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。

公开(公告)号：US20080144364A1

公开(公告)日：2008-06-19

申请号：US12002668

申请日：2007-12-18

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： G11C11/50 ,  H01L21/00

CPC分类号： H01L29/788 ,  G11C11/56 ,  G11C23/00

摘要： There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

摘要翻译： 提供了能够增强或最大化存储器件的集成度的多位机电存储器件以及制造多位机电存储器件的方法，该多位机电存储器件包括衬底，衬底上的位线，并且在 第一个方向 位线上的字线，与位线绝缘，并且沿与第一方向横切的第二方向延伸，以及包括形状记忆合金的悬臂电极。 所述悬臂电极具有电连接到所述位线的第一部分和沿所述第一方向延伸的第二部分，并且通过气隙与所述字线间隔开，其中所述悬臂电极在第一状态下与所述第一状态电接触 字线，并且在第二状态下与字线间隔开。