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1.发明授权公开(公告)号：US09710047B2
公开(公告)日：2017-07-18
申请号：US14572854
申请日：2014-12-17
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3296 , G06F9/45533 , G06F13/1657 , Y02D10/126 , Y02D10/26 , Y02D10/28
摘要： An information processing apparatus connected to another information processing apparatus includes an arithmetic processing device, and one or more processors configured to detect an exception event of a self main memory when the arithmetic processing device requests an access to data on a main memory possessed by the another information processing apparatus and vary a clock frequency or a voltage of the arithmetic processing device on the basis of the detection of the exception event.
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公开(公告)号：US20230010895A1
公开(公告)日：2023-01-12
申请号：US17708020
申请日：2022-03-30
申请人： FUJITSU LIMITED
发明人： Shingo OKUNO , Masahiro Miwa
IPC分类号： G06F9/50
摘要： An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: divide a job in units of computing nodes for a plurality of computing nodes; determine execution of scale-out or scale-in on the basis of a load in a case where each of the computing nodes is caused to execute a job obtained by the division; execute, in a case where determining execution of the scale-out, the scale-out according to the division of the job in units of computing nodes; and execute, in a case where determining execution of the scale-in, the scale-in according to the division of the job in units of computing nodes.
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公开(公告)号：US20220180161A1
公开(公告)日：2022-06-09
申请号：US17488356
申请日：2021-09-29
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
摘要： An arithmetic processing apparatus includes a plurality of processors; and one or more processors configured to execute a training of a deep neural network by the plurality of processors in parallel by allocating a plurality of processes to the plurality of processors, aggregate a plurality of variable update information that are used respectively used for updating a plurality of variables of the deep neural network and are obtained by the training by each of the plurality of processes, between the plurality of processes for each of the plurality of variables, and determine whether superior or not the training by a certain number of processes that is less than the number of processes of the plurality of processes is, based on first variable update information that is variable update information aggregated between the plurality of processes and second variable update information that is variable update information during the aggregating.
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公开(公告)号：US10855610B2
公开(公告)日：2020-12-01
申请号：US16057865
申请日：2018-08-08
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
IPC分类号： H04L12/741 , H04L12/805 , H04L12/835 , H04L12/721 , H04L12/707 , H04L12/947
摘要： An information processing apparatus includes a memory; and a processor coupled to the memory and configured to determine whether a size of data is equal to a predetermined threshold or less when degradation occurs on a communication path to a destination information processing apparatus of the data; transmit the data to another information processing apparatus different from the destination information processing apparatus and coupled to the destination information processing apparatus when it is determined that the size of the data is more than the predetermined threshold; and transmit the data to the destination information processing apparatus through the communication path when it is determined that the size of the data is the predetermined threshold or less.
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公开(公告)号：US20200337114A1
公开(公告)日：2020-10-22
申请号：US16830655
申请日：2020-03-26
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
摘要： In a system including a plurality of nodes, a plurality of first relay devices, and a plurality of second relay devices, where each first relay device is connected to two or more second relay devices, the nodes are classified into a plurality of groups such that different nodes individually connected to different first relay devices having different sets of second relay devices connected thereto are classified into different groups. A representative node is selected from each group. Communication order of first internode communication performed between the representative nodes is determined such that data is transferred according to a first tree, in parallel with which different data is transferred according to a second tree. Communication order of second internode communication performed for each group is determined such that data is transferred according to a third tree, in parallel with which different data is transferred according to a fourth tree.
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公开(公告)号：US20170300102A1
公开(公告)日：2017-10-19
申请号：US15484373
申请日：2017-04-11
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/329 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/24
摘要： An information processing device includes: a memory; and a processor coupled to the memory. The processor is configured to: set a first limit value of power consumption that the processor is permitted to consume during execution of a program to be analyzed, control execution of the program, control the processor to enable a generation of at least one interrupt during the execution of the program, acquire executed function information indicating a currently executed function included in the program and a first operational frequency of the processor during the execution of the function included in the program, and output the executed function information and limit information indicating whether the first operational frequency of the processor was limited by the first limit value to the memory.
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公开(公告)号：US20160352824A1
公开(公告)日：2016-12-01
申请号：US15137221
申请日：2016-04-25
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa , Kohta Nakashima
IPC分类号： H04L29/08
CPC分类号： H04L67/1044 , H04L67/10
摘要： A system is a multi-layered fullmesh system in which layers of fullmesh systems, having Leaf switches fullmesh-coupled to each other, are coupled to each other, the system including nodes and performing applications, at least one of nodes being coupled to each of the Leaf switches. The parallel processing system includes circuitry configured to: compare communication recording information in which a number of times of communication between nodes during execution of an application is recorded with communication pattern information in which assignment information indicating which nodes having an intra-layer or inter-layer connection relationship with a Leaf switch are assigned is specified for each communication pattern; extract assignment information of a communication pattern which is the most similar to communication indicated by the communication recording information, based on the communication pattern information; and assign nodes that subsequently execute the application, based on the extracted assignment information.
摘要翻译： 一种系统是一种多层全网系统，其中具有彼此全互联的Leaf交换机的全网系统层彼此耦合，所述系统包括节点和执行应用，至少一个节点被耦合到每个节点 叶子开关。 并行处理系统包括：电路，其被配置为：比较通信记录信息，其中记录在执行应用期间的节点之间的通信次数与通信模式信息，其中分配信息指示哪些节点具有层内或层间 为每个通信模式指定与叶片开关的连接关系; 基于通信模式信息提取与通信记录信息指示的通信最相似的通信模式的分配信息; 并且基于所提取的分配信息来分配随后执行所述应用的节点。
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公开(公告)号：US10281971B2
公开(公告)日：2019-05-07
申请号：US15484373
申请日：2017-04-11
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
IPC分类号： G06F1/32 , G06F1/324 , G06F1/3234 , G06F1/329 , G06F9/50 , G06F1/3203
摘要： An information processing device includes: a memory; and a processor coupled to the memory. The processor is configured to: set a first limit value of power consumption that the processor is permitted to consume during execution of a program to be analyzed, control execution of the program, control the processor to enable a generation of at least one interrupt during the execution of the program, acquire executed function information indicating a currently executed function included in the program and a first operational frequency of the processor during the execution of the function included in the program, and output the executed function information and limit information indicating whether the first operational frequency of the processor was limited by the first limit value to the memory.
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9.发明申请公开(公告)号：US20190052573A1
公开(公告)日：2019-02-14
申请号：US16057865
申请日：2018-08-08
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
IPC分类号： H04L12/805 , H04L12/835 , H04L12/947 , H04L12/707 , H04L12/721
摘要： An information processing apparatus includes a memory; and a processor coupled to the memory and configured to determine whether a size of data is equal to a predetermined threshold or less when degradation occurs on a communication path to a destination information processing apparatus of the data; transmit the data to another information processing apparatus different from the destination information processing apparatus and coupled to the destination information processing apparatus when it is determined that the size of the data is more than the predetermined threshold; and transmit the data to the destination information processing apparatus through the communication path when it is determined that the size of the data is the predetermined threshold or less.
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公开(公告)号：US20190018704A1
公开(公告)日：2019-01-17
申请号：US16029140
申请日：2018-07-06
申请人： FUJITSU LIMITED
发明人： Masahiro Miwa
摘要： A job assignment apparatus includes a processor configured to perform assignment of a first job to a first arithmetic device and a second arithmetic device in such a way that data is transmitted in a first direction, the first job being processed in a process algorithm in which a plurality of arithmetic devices sequentially transmit data, the first arithmetic device being connected to the second arithmetic device via a first switch and a second switch, the first direction being a direction from the first switch to the second switch, and perform assignment of a second job to a third arithmetic device and a fourth arithmetic device in such a way that data is transmitted in a second direction, the third arithmetic device being connected to the fourth arithmetic device via the first switch and the second switch, the second direction being a different direction from the first direction.
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