公开(公告)号：US08772847B2

公开(公告)日：2014-07-08

申请号：US13687715

申请日：2012-11-28

申请人： Fujitsu Semiconductor Limited

发明人： Naoya Sashida

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76849 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.

摘要翻译： 半导体器件包括半导体衬底; 形成在半导体衬底上的第一绝缘膜; 形成在第一绝缘膜上并通过依次层叠下电极，电容器电介质膜和上电极而形成的电容器; 形成在所述电容器上并且在俯视图中具有包括所述上部电极的整个区域的孔的第二绝缘膜; 以及形成在孔中并包含钨的导体插塞。

公开(公告)号：US09508559B2

公开(公告)日：2016-11-29

申请号：US14030662

申请日：2013-09-18

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Shoko Saito ,  Tomoyuki Okada ,  Kanji Takeuchi ,  Mitsufumi Naoe ,  Masahiko Minemura ,  Yukihiro Sato ,  Yoshito Konno ,  Yasuhiko Inada ,  Tomoaki Inaoka ,  Naoya Sashida

IPC分类号： G01R31/28 ,  H01L29/00 ,  H01L21/308 ,  H01L21/3213 ,  H01L23/544 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L21/308 ,  H01L21/32139 ,  H01L23/522 ,  H01L23/544 ,  H01L24/05 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02166 ,  H01L2224/05556

摘要： A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.

摘要翻译： 一种半导体晶片，包括分别转移到半导体晶片的多个照射区域的图案，多个芯片区域分别形成在多个照射区域中，多个第一虚设图案分别形成在多个第一芯片区域中 所述多个第一虚设图案以第一方式重复布置，多个第二虚设图案分别形成在所述多个照射区域中的每一个的多个芯片区域的第二芯片区域中 多个拍摄区域，多个第二虚拟图案以与第一方式不同的第二方式重复布置。

公开(公告)号：US08735954B2

公开(公告)日：2014-05-27

申请号：US13687715

申请日：2012-11-28

申请人： Fujitsu Semiconductor Limited

发明人： Naoya Sashida

IPC分类号： H01L21/02

摘要： A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.

公开(公告)号：US20160268272A1

公开(公告)日：2016-09-15

申请号：US15163564

申请日：2016-05-24

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L27/115

CPC分类号： H01L27/11507 ,  G11C11/221

摘要： An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

公开(公告)号：US20150221657A1

公开(公告)日：2015-08-06

申请号：US14601499

申请日：2015-01-21

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L27/115

CPC分类号： H01L27/11507 ,  G11C11/221

摘要： An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

摘要翻译： 半导体器件的实施例包括连接到从多个铁电电容器选择的铁电电容器的板线，并且从顶部电极覆盖所选择的铁电电容器和选定的铁电电容器之间的区域。

公开(公告)号：US20130295693A1

公开(公告)日：2013-11-07

申请号：US13930095

申请日：2013-06-28

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76876 ,  H01L21/76877 ,  H01L27/11507 ,  H01L27/228 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75 ,  H01L2924/19041

摘要： A semiconductor device with a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing an upper surface of the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film.

摘要翻译： 一种具有功能元件的半导体器件，包括由导电金属氧化物构成的上电极并被构造成存储信息; 覆盖功能元件的层间绝缘膜; 形成在所述层间绝缘膜中的接触孔，所述接触孔包括侧壁表面和底部，并且在底部暴露所述上电极的上表面; 覆盖接触孔的底部和侧壁表面的导电阻挡膜; 以及形成在所述导电阻挡膜上的钨膜，所述钨膜填充所述接触孔的至少一部分，其中在所述钨膜和所述导电阻挡膜之间的界面处形成硅原子浓缩的层。

公开(公告)号：US20130168813A1

公开(公告)日：2013-07-04

申请号：US13687715

申请日：2012-11-28

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L49/02

CPC分类号： H01L28/60 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76849 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.

摘要翻译： 半导体器件包括半导体衬底; 形成在半导体衬底上的第一绝缘膜; 形成在第一绝缘膜上并通过依次层叠下电极，电容器电介质膜和上电极而形成的电容器; 形成在所述电容器上并且在俯视图中具有包括所述上部电极的整个区域的孔的第二绝缘膜; 以及形成在孔中并包含钨的导体插塞。

公开(公告)号：US09773794B2

公开(公告)日：2017-09-26

申请号：US15163564

申请日：2016-05-24

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L21/8244 ,  H01L27/11507 ,  G11C11/22

CPC分类号： H01L27/11507 ,  G11C11/221

摘要： An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

公开(公告)号：US09373626B2

公开(公告)日：2016-06-21

申请号：US14601499

申请日：2015-01-21

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Naoya Sashida

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L27/115 ,  G11C11/22

CPC分类号： H01L27/11507 ,  G11C11/221

摘要： An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

摘要翻译： 半导体器件的实施例包括连接到从多个铁电电容器选择的铁电电容器的板线，并且从顶部电极覆盖所选择的铁电电容器和选定的铁电电容器之间的区域。