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公开(公告)号：US20070138632A1
公开(公告)日：2007-06-21
申请号：US11642439
申请日：2006-12-19
IPC分类号： H01L23/34
CPC分类号： H05K3/3452 , H05K3/284 , H05K3/303 , H05K2201/0989 , H05K2201/10636 , H05K2201/10727 , H05K2201/2036 , Y02P70/611 , Y02P70/613
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.
摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 在保护层中形成开口以暴露每个配对接合焊盘的至少三个侧面。 保护层包括至少一个独立的残留部分，位于开口内和成对的接合焊盘之间，使得电子部件安装在独立的残留部分上并电连接到接合焊盘。 在电子部件和载体之间形成没有死空间的凹槽，使得用于封装电子部件的模制化合物可以流过凹槽以填充开口和电子部件下方的空间，并将至少三个侧面 每个接合垫。
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公开(公告)号：US20070202633A1
公开(公告)日：2007-08-30
申请号：US11651708
申请日：2007-01-09
申请人： Wen-Tsung Tseng , Fang-Lin Tsai , Ho-Yi Tsai , Cheng-Hsu Hsiao , Chih-Ming Huang
发明人： Wen-Tsung Tseng , Fang-Lin Tsai , Ho-Yi Tsai , Cheng-Hsu Hsiao , Chih-Ming Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/4882 , H01L23/3675 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2223/5442 , H01L2223/54473 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/01079 , H01L2924/16152 , H01L2924/16315 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： A semiconductor package and a method for fabricating the same are provided. The method includes providing a substrate having recognition points and a heat sink having openings, and placing the heat sink on the substrate with the recognition points being exposed through the openings; using a checking system to inspect the recognition points through the openings so as to ensure that the heat sink is placed at a predetermined position on the substrate; and attaching the heat sink to the substrate via an adhesive. By the above semiconductor package and method, there is no need to form positioning holes in the substrate such that any adverse effect on the circuit layout and reliability of the semiconductor package is avoided, and any positional shifting of the heat sink relative to the substrate can be determined in a real time manner.
摘要翻译： 提供半导体封装及其制造方法。 该方法包括提供具有识别点的基板和具有开口的散热器，并且将散热器放置在基板上，识别点通过开口露出; 使用检查系统通过开口检查识别点，以确保散热器被放置在基板上的预定位置; 以及通过粘合剂将散热器附接到基板。 通过上述半导体封装和方法，不需要在衬底中形成定位孔，从而避免对半导体封装的电路布局和可靠性的任何不利影响，并且散热片相对于衬底的任何位置偏移可以 以实时的方式确定。
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公开(公告)号：US08013443B2
公开(公告)日：2011-09-06
申请号：US12727307
申请日：2010-03-19
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
CPC分类号： H01L23/3121 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H05K3/284 , H05K3/3442 , H05K3/3452 , H05K2201/0989 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.
摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。
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公开(公告)号：US20100170709A1
公开(公告)日：2010-07-08
申请号：US12727307
申请日：2010-03-19
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
CPC分类号： H01L23/3121 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H05K3/284 , H05K3/3442 , H05K3/3452 , H05K2201/0989 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.
摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。
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公开(公告)号：US07696623B2
公开(公告)日：2010-04-13
申请号：US11643147
申请日：2006-12-20
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
CPC分类号： H01L23/3121 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H05K3/284 , H05K3/3442 , H05K3/3452 , H05K2201/0989 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.
摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。
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公开(公告)号：US20070145561A1
公开(公告)日：2007-06-28
申请号：US11643147
申请日：2006-12-20
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang
IPC分类号： H01L23/02
CPC分类号： H01L23/3121 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H05K3/284 , H05K3/3442 , H05K3/3452 , H05K2201/0989 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.
摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。
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7.发明授权Stack structure of semiconductor packages and method for fabricating the stack structure 有权半导体封装的堆叠结构和制造堆叠结构的方法公开(公告)号：US07855443B2
公开(公告)日：2010-12-21
申请号：US11732853
申请日：2007-04-04
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。
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公开(公告)号：US20110070697A1
公开(公告)日：2011-03-24
申请号：US12955256
申请日：2010-11-29
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L21/48
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置相对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。
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公开(公告)号：US08420521B2
公开(公告)日：2013-04-16
申请号：US12955256
申请日：2010-11-29
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
IPC分类号： H01L21/44
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。
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10.发明申请Stack structure of semiconductor packages and method for fabricating the stack structure 有权半导体封装的堆叠结构和制造堆叠结构的方法公开(公告)号：US20070246811A1
公开(公告)日：2007-10-25
申请号：US11732853
申请日：2007-04-04
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
CPC分类号： H01L25/105 , H01L23/49811 , H01L23/49838 , H01L24/73 , H01L25/50 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/01077 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。
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