公开(公告)号：US06794706B2

公开(公告)日：2004-09-21

申请号：US10064493

申请日：2002-07-22

申请人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

发明人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/28194 ,  H01L21/3144 ,  H01L28/40 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

摘要翻译： 一种在氮化物层上具有再氧化物层的电容器结构，其中氮化物层和再氧化物层之间的界面包括电子阱。 载波阱的特性控制器件的电压输出。 氮化物层和再氧化物层的厚度也控制电压输出。 氮化物层和再氧化物层形成介质电容器。 介质电容器经历陷阱填充极限电压，其中为多个电流输出一致的电压。

公开(公告)号：US08749293B2

公开(公告)日：2014-06-10

申请号：US13529557

申请日：2012-06-21

申请人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

IPC分类号： G06G7/19 ,  H01L29/00

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

公开(公告)号：US20120261724A1

公开(公告)日：2012-10-18

申请号：US13529557

申请日：2012-06-21

申请人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

IPC分类号： H01L23/52 ,  H01L21/326

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

公开(公告)号：US07500208B2

公开(公告)日：2009-03-03

申请号：US11673369

申请日：2007-02-09

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US07231617B2

公开(公告)日：2007-06-12

申请号：US10711418

申请日：2004-09-17

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC分类号： G06F17/50

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 可以在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US06445021B1

公开(公告)日：2002-09-03

申请号：US09665913

申请日：2000-09-20

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L27148

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

公开(公告)号：US08405135B2

公开(公告)日：2013-03-26

申请号：US12898340

申请日：2010-10-05

申请人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

发明人： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

IPC分类号： H01L27/108

CPC分类号： H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

摘要翻译： 本发明提供一种3D通孔电容器及其形成方法。 电容器包括在基板上的绝缘层。 绝缘层具有通孔，其具有侧壁和底部。 第一电极覆盖通孔的侧壁和底部的至少一部分。 第一高k电介质材料层覆盖在第一电极上。 第一导电板在第一高k电介质材料层之上。 第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。 在通孔的剩余部分中形成第二电极。 第一导电板基本上平行于第一电极并且不与第一和第二电极接触。 还提供了这种3D通孔电容器的阵列。

公开(公告)号：US20070103228A1

公开(公告)日：2007-05-10

申请号：US11161932

申请日：2005-08-23

申请人： Fen Chen ,  Douglas Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas Coolbaugh ,  Baozhen Li

IPC分类号： H01L25/00

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

公开(公告)号：US06743655B2

公开(公告)日：2004-06-01

申请号：US10205527

申请日：2002-07-25

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L2100

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

摘要翻译： 描述了在偏压和照明时呈现光诱导的负微分电阻区域的光电二极管。 光电二极管包括N +硅衬底，形成在N +硅衬底上的氮化硅层，形成在氮化硅层上的再氧化氮化物层和形成在再氧化氮化物层的至少一部分上的N +多晶硅层。

公开(公告)号：US08294505B2

公开(公告)日：2012-10-23

申请号：US11161932

申请日：2005-08-23

申请人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

发明人： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

IPC分类号： G06G7/19 ,  H01L29/00

CPC分类号： H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

摘要翻译： 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。