公开(公告)号：US06794706B2

公开(公告)日：2004-09-21

申请号：US10064493

申请日：2002-07-22

申请人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

发明人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/28194 ,  H01L21/3144 ,  H01L28/40 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

摘要翻译： 一种在氮化物层上具有再氧化物层的电容器结构，其中氮化物层和再氧化物层之间的界面包括电子阱。 载波阱的特性控制器件的电压输出。 氮化物层和再氧化物层的厚度也控制电压输出。 氮化物层和再氧化物层形成介质电容器。 介质电容器经历陷阱填充极限电压，其中为多个电流输出一致的电压。

公开(公告)号：US08926805B2

公开(公告)日：2015-01-06

申请号：US13561599

申请日：2012-07-30

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D17/02 ,  C25D5/18 ,  C25D5/02 ,  H01L21/288 ,  C25D17/00 ,  H01L21/762

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07667278B2

公开(公告)日：2010-02-23

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括包括包括金属碳化物的栅电极和至少一种制造方法的至少一个FET的互补金属氧化物半导体（CMOS）的半导体器件。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US07598545B2

公开(公告)日：2009-10-06

申请号：US11111592

申请日：2005-04-21

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：US20090179279A1

公开(公告)日：2009-07-16

申请号：US12014511

申请日：2008-01-15

申请人： Veeraraghavan S. Basker ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Lubomyr T. Romankiw

发明人： Veeraraghavan S. Basker ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Lubomyr T. Romankiw

IPC分类号： H01L21/283 ,  H01L29/43 ,  C25D3/00

CPC分类号： C25D3/567 ,  C25D5/02 ,  C25D7/12 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof.

摘要翻译： 公开了用于互补金属氧化物半导体（“CMOS”）应用的稳定金属栅极电极和制造稳定的金属栅电极的方法。 具体地说，金属栅电极通过合金化来稳定化，其中合金包括选自Re，Ru，Pt，Rh，Ni，Al及其组合的金属和选自W，V，Ti ，Ta及其组合。

公开(公告)号：US20090127121A1

公开(公告)日：2009-05-21

申请号：US11940720

申请日：2007-11-15

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D5/00 ,  C25D17/00

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US20080258198A1

公开(公告)日：2008-10-23

申请号：US12166690

申请日：2008-07-02

申请人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/76

CPC分类号： H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising: a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供了一种金属叠层，包括：铪基电介质; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

公开(公告)号：US20080026551A1

公开(公告)日：2008-01-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

发明人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

IPC分类号： H01L21/3205

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US20070090471A1

公开(公告)日：2007-04-26

申请号：US11259644

申请日：2005-10-26

申请人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

发明人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。