公开(公告)号：US20140167711A1

公开(公告)日：2014-06-19

申请号：US13720050

申请日：2012-12-19

申请人： Fenardi Thenus ,  Peng Zou ,  Joseph T. Dibene, II

发明人： Fenardi Thenus ,  Peng Zou ,  Joseph T. Dibene, II

IPC分类号： G05F1/46

CPC分类号： G05F1/468 ,  H02M3/1584

摘要： In some embodiments described herein, proposed schemes utilize a duty-cycle sensing technique to detect load current imbalance in each individual inductor, and then adjusts the duty cycles for the specific phases through a digital duty cycle tuner.

摘要翻译： 在本文描述的一些实施例中，所提出的方案利用占空比感测技术来检测每个单独电感器中的负载电流不平衡，然后通过数字占空比调谐器调整特定相位的占空比。

公开(公告)号：US20110154071A1

公开(公告)日：2011-06-23

申请号：US12641916

申请日：2009-12-18

申请人： Peng Zou ,  Joseph T. Dibene, II ,  Fenardi Thenus

发明人： Peng Zou ,  Joseph T. Dibene, II ,  Fenardi Thenus

IPC分类号： G06F1/32

CPC分类号： G06F1/3203

摘要： Embodiments of an apparatus, system and method are described for dynamically time-interleaving supply voltage modulation to shape a power profile. An apparatus may comprise, for example, a power management module to monitor power information received from a plurality of devices and send a power control signal including delay information to each device having power information that exceeds a power threshold, the delay information comprising information for time-interleaving power usage among the devices having power information that exceeds the power threshold. Other embodiments are described and claimed.

摘要翻译： 描述了用于动态时间交织电源电压调制以形成功率分布的装置，系统和方法的实施例。 装置可以包括例如电力管理模块，用于监视从多个设备接收的功率信息，并向包括超过功率阈值的功率信息的每个设备发送包括延迟信息的功率控制信号，延迟信息包括时间信息 在具有超过功率阈值的功率信息的设备之间交换功率使用。 描述和要求保护其他实施例。

公开(公告)号：US08856564B2

公开(公告)日：2014-10-07

申请号：US12641916

申请日：2009-12-18

申请人： Peng Zou ,  Joseph T Dibene, II ,  Fenardi Thenus

发明人： Peng Zou ,  Joseph T Dibene, II ,  Fenardi Thenus

IPC分类号： G06F1/32

CPC分类号： G06F1/3203

摘要： Embodiments of an apparatus, system and method are described for dynamically time-interleaving supply voltage modulation to shape a power profile. An apparatus may comprise, for example, a power management module to monitor power information received from a plurality of devices and send a power control signal including delay information to each device having power information that exceeds a power threshold, the delay information comprising information for time-interleaving power usage among the devices having power information that exceeds the power threshold. Other embodiments are described and claimed.

摘要翻译： 描述了用于动态时间交织电源电压调制以形成功率分布的装置，系统和方法的实施例。 装置可以包括例如电力管理模块，用于监视从多个设备接收的功率信息，并向包括超过功率阈值的功率信息的每个设备发送包括延迟信息的功率控制信号，延迟信息包括时间信息 在具有超过功率阈值的功率信息的设备之间交换功率使用。 描述和要求保护其他实施例。

公开(公告)号：US20140070846A1

公开(公告)日：2014-03-13

申请号：US13613810

申请日：2012-09-13

申请人： Peng Zou ,  Fenardi Thenus ,  David J. Harriman

发明人： Peng Zou ,  Fenardi Thenus ,  David J. Harriman

IPC分类号： H03K19/0175

CPC分类号： G01R31/31924

摘要： In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，测试装置包括现场可编程门阵列（FPGA），其包括根据当前模式逻辑（CML）信令来传送第一信号的第一发射机和根据CML信令接收第二信号的第一接收机，以及接口 电路将FPGA耦合到根据电压模式信号进行通信的设备。 接口电路可以将根据CML信令的由第一发射机传送的第一信号适配成电压模式信令信号，以供设备接收。 描述和要求保护其他实施例。

公开(公告)号：US20110161683A1

公开(公告)日：2011-06-30

申请号：US12724084

申请日：2010-03-15

申请人： Peng Zou ,  Joseph T. Dibene, II ,  Fernardi Thenus

发明人： Peng Zou ,  Joseph T. Dibene, II ,  Fernardi Thenus

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/266 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D10/172

摘要： In some embodiments, the invention provides a higher efficiency, real-time platform power management architecture for computing platforms. A more direct power management architecture may be provided using integrated voltage regulators and in some embodiments, a direct power management interface (DPMI) as well. Integrated voltage regulators, such as in-silicon voltage regulators (ISVR) can be used to implement quicker, more highly responsive power state transitions.

摘要翻译： 在一些实施例中，本发明为计算平台提供了更高效率的实时平台电源管理架构。 可以使用集成稳压器提供更直接的功率管理架构，并且在一些实施例中也可以提供直接功率管理接口（DPMI）。 集成稳压器，例如硅片内稳压器（ISVR）可用于实现更快，更高响应的功率状态转换。

公开(公告)号：US09711108B2

公开(公告)日：2017-07-18

申请号：US14129269

申请日：2013-06-10

申请人： Fenardi Thenus ,  Peng Zou ,  Raghu Nandan Chepuri ,  Henry K. Koertzen

发明人： Fenardi Thenus ,  Peng Zou ,  Raghu Nandan Chepuri ,  Henry K. Koertzen

IPC分类号： G09G5/00 ,  H02M3/158 ,  G06F3/041 ,  H03K5/14 ,  H03K7/06 ,  H03K7/08 ,  H03K17/284 ,  H02M1/00

CPC分类号： G09G5/006 ,  G06F3/0412 ,  G09G2330/021 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2003/1586 ,  H03K5/14 ,  H03K7/06 ,  H03K7/08 ,  H03K17/284 ,  Y02B70/16

摘要： Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.

公开(公告)号：US08990591B2

公开(公告)日：2015-03-24

申请号：US12724084

申请日：2010-03-15

申请人： Peng Zou ,  Joseph T. Dibene, II ,  Fernardi Thenus

发明人： Peng Zou ,  Joseph T. Dibene, II ,  Fernardi Thenus

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/266 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D10/172

摘要： In some embodiments, the invention provides a higher efficiency, real-time platform power management architecture for computing platforms. A more direct power management architecture may be provided using integrated voltage regulators and in some embodiments, a direct power management interface (DPMI) as well. Integrated voltage regulators, such as in-silicon voltage regulators (ISVR) can be used to implement quicker, more highly responsive power state transitions.

摘要翻译： 在一些实施例中，本发明为计算平台提供了更高效率的实时平台电源管理架构。 可以使用集成稳压器提供更直接的功率管理架构，并且在一些实施例中也可以提供直接功率管理接口（DPMI）。 集成稳压器，例如硅片内稳压器（ISVR）可用于实现更快，更高响应的功率状态转换。

公开(公告)号：US08872546B2

公开(公告)日：2014-10-28

申请号：US13613810

申请日：2012-09-13

申请人： Peng Zou ,  Fenardi Thenus ,  David J. Harriman

发明人： Peng Zou ,  Fenardi Thenus ,  David J. Harriman

IPC分类号： H03K19/0175

CPC分类号： G01R31/31924

摘要： In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，测试装置包括现场可编程门阵列（FPGA），其包括根据当前模式逻辑（CML）信令来传送第一信号的第一发射机和根据CML信令接收第二信号的第一接收机，以及接口 电路将FPGA耦合到根据电压模式信号进行通信的设备。 接口电路可以将根据CML信令的由第一发射机传送的第一信号适配成电压模式信令信号，以供设备接收。 描述和要求保护其他实施例。

公开(公告)号：US20080101450A1

公开(公告)日：2008-05-01

申请号：US11586920

申请日：2006-10-26

申请人： Zuoguo Wu ,  Peng Zou ,  Fenardi Thenus

发明人： Zuoguo Wu ,  Peng Zou ,  Fenardi Thenus

IPC分类号： H03K5/159

CPC分类号： H04L25/03878 ,  H04L7/0054 ,  H04L7/0337 ,  H04L25/0272

摘要： According to some embodiments, a continuous time linear equalization circuit includes an input of a first stage to receive a differential input signal, and an output of the first stage to output a differential output signal. A transfer function between the input and the output exhibits two zeros and three poles in frequency domain, and the differential output signal is not fed back to the first stage.

摘要翻译： 根据一些实施例，连续时间线性均衡电路包括用于接收差分输入信号的第一级的输入和第一级的输出以输出差分输出信号。 输入和输出之间的传递函数在频域中显示两个零和三极，差分输出信号不反馈到第一级。

公开(公告)号：US08539781B2

公开(公告)日：2013-09-24

申请号：US12666208

申请日：2008-06-22

申请人： J. Donald Carruthers ,  Karl Boggs ,  Luping Wang ,  Shaun Wilson ,  Jose I. Arno ,  Paul J. Marganski ,  Steven M. Bilodeau ,  Peng Zou ,  Brian Bobita ,  Joseph D. Sweeney ,  Douglas Edwards

发明人： J. Donald Carruthers ,  Karl Boggs ,  Luping Wang ,  Shaun Wilson ,  Jose I. Arno ,  Paul J. Marganski ,  Steven M. Bilodeau ,  Peng Zou ,  Brian Bobita ,  Joseph D. Sweeney ,  Douglas Edwards

IPC分类号： F25B15/00

CPC分类号： B01J20/26 ,  B01J20/20 ,  B01J20/28054 ,  B01J20/28092 ,  B01J20/30 ,  B01J20/305 ,  B01J20/3078 ,  B01J2220/445 ,  C09K5/047 ,  F25B17/08 ,  F25B27/007 ,  F25B35/04 ,  F25B37/00 ,  F25B2500/01

摘要： An adsorption structure is described that includes at least one adsorbent member formed of an adsorbent material and at least one porous member provided in contact with a portion of the adsorbent member to allow gas to enter and exit the portion of the adsorbent member. Such adsorption structure is usefully employed in adsorbent-based refrigeration systems. A method also is described for producing an adsorbent material, in which a first polymeric material is provided having a first density and a second polymeric material is provided having a second density, in which the second polymeric material is in contact with the first polymeric material to form a structure. The structure is pyrolyzed to form a porous adsorbent material including a first region corresponding to the first polymeric material and a second region corresponding to the second polymeric material, in which at least one of the pore sizes and the pore distribution differs between the first region and the second region.

摘要翻译： 描述了吸附结构，其包括由吸附剂材料形成的至少一个吸附构件和与吸附构件的一部分接触设置的至少一个多孔构件，以允许气体进入和离开吸附构件的该部分。 这种吸附结构在吸附剂型制冷系统中有用。 描述了一种用于生产吸附材料的方法，其中提供具有第一密度的第一聚合物材料和第二聚合物材料，其具有第二密度，其中第二聚合物材料与第一聚合物材料接触， 形成一个结构。 该结构被热解以形成多孔吸附剂材料，其包括对应于第一聚合物材料的第一区域和对应于第二聚合物材料的第二区域，其中孔径和孔分布中的至少一个在第一区域和第 第二个地区。