公开(公告)号：US06489219B1

公开(公告)日：2002-12-03

申请号：US08555801

申请日：1995-11-09

申请人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

发明人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

IPC分类号： H01L21324

CPC分类号： H01L28/40 ,  H01L21/324 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： An improved method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is then deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed of the substrate is optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be used after deposition of a metal layer, or at other process steps as desired.

摘要翻译： 一种用于合金化半导体衬底的改进方法，其上已经形成了封闭在间隔物中的字线，衬底暴露在字线之间。 然后在衬底和字线上沉积薄的密封层，密封层有助于将合金保持在所述衬底中。 所用基板的合金材料可以是单原子氢。 将基底与单原子氢合金也可以在沉积金属层之后使用，或者根据需要在其它工艺步骤中使用。

公开(公告)号：US06664171B2

公开(公告)日：2003-12-16

申请号：US10304194

申请日：2002-11-25

申请人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

发明人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

IPC分类号： H01L21324

CPC分类号： H01L28/40 ,  H01L21/324 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.

公开(公告)号：US06342435B1

公开(公告)日：2002-01-29

申请号：US09441925

申请日：1999-11-17

申请人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

发明人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

IPC分类号： H01L21324

CPC分类号： H01L21/823892 ,  H01L21/2253

摘要： Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

摘要翻译： 公开了一种改进的CMOS制造方法，其允许在单个工艺步骤中同时，驱动退火和剥离裸硅晶片中的注入阱。 更具体地，使用非惰性环境环境来实现单级驱动退火 - 脱模（DAD）工艺。 DAD过程在氩/氢环境的组合环境中完成。 该方法使得硅晶片稍微粗糙化，随后进行氧化步骤，其可选地在氩气/氧气环境环境中进行，以平滑硅表面。 氧化步骤还可以任选地用作氧化垫或筛选氧化物用于随后的制造。

公开(公告)号：US6072226A

公开(公告)日：2000-06-06

申请号：US844169

申请日：1997-04-18

申请人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

发明人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/31053 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31658 ,  H01L21/76216 ,  Y10S438/978

摘要： A method for forming a field isolation structure and an improved field isolation structure are provided. The method includes forming a field oxide on a silicon substrate using an ozone enhanced local oxidation of silicon (LOCOS) process. Following formation of the field oxide a surface topography of the field oxide is sloped or tapered by ion milling, dry etching, reactive ion etching or chemical mechanical planarization. With an ozone enhanced LOCOS process, oxidation rates are increased and stress between the field oxide and substrate are reduced. This permits the formation of field isolation structures with reduced lateral encroachment and a smaller bird's beak area. In addition, the sloped topography of the field oxide permits a subsequently deposited conductive layer (e.g., polysilicon) to be etched without the formation of conductive stringers. During the etch process the active areas on the substrate can be protected with a sacrificial oxide or by only partially removing the LOCOS mask.

摘要翻译： 提供了一种用于形成场隔离结构和改进的场隔离结构的方法。 该方法包括使用臭氧增强的局部氧化硅（LOCOS）工艺在硅衬底上形成场氧化物。 在形成场氧化物之后，场氧化物的表面形貌通过离子研磨，干蚀刻，反应离子蚀刻或化学机械平面化而倾斜或渐缩。 通过臭氧增强的LOCOS工艺，氧化速率增加，场氧化物和衬底之间的应力降低。 这允许形成具有减小的横向侵入和较小鸟喙面积的场隔离结构。 此外，场氧化物的倾斜形貌允许随后沉积的导电层（例如，多晶硅）被蚀刻而不形成导电桁条。 在蚀刻过程中，可以用牺牲氧化物或仅部分去除LOCOS掩模来保护衬底上的有源区域。

公开(公告)号：US5672539A

公开(公告)日：1997-09-30

申请号：US538732

申请日：1995-10-03

申请人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

发明人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31658 ,  H01L21/76216 ,  Y10S438/978

摘要： A method for forming a field isolation structure and an improved field isolation structure are provided. The method includes forming a field oxide on a silicon substrate using an ozone enhanced local oxidation of silicon (LOCOS) process. Following formation of the field oxide a surface topography of the field oxide is sloped or tapered by ion milling, dry etching, reactive ion etching or chemical mechanical planarization. With an ozone enhanced LOCOS process, oxidation rates are increased and stress between the field oxide and substrate are reduced. This permits the formation of field isolation structures with reduced lateral encroachment and a smaller bird's beak area. In addition, the sloped topography of the field oxide permits a subsequently deposited conductive layer (e.g., polysilicon) to be etched without the formation of conductive stringers. During the etch process the active areas on the substrate can be protected with a sacrificial oxide or by only partially removing the LOCOS mask.

摘要翻译： 提供了一种用于形成场隔离结构和改进的场隔离结构的方法。 该方法包括使用臭氧增强的局部氧化硅（LOCOS）工艺在硅衬底上形成场氧化物。 在形成场氧化物之后，场氧化物的表面形貌通过离子研磨，干蚀刻，反应离子蚀刻或化学机械平面化而倾斜或渐缩。 通过臭氧增强的LOCOS工艺，氧化速率增加，场氧化物和衬底之间的应力降低。 这允许形成具有减小的横向侵入和较小鸟喙面积的场隔离结构。 此外，场氧化物的倾斜形貌允许随后沉积的导电层（例如，多晶硅）被蚀刻而不形成导电桁条。 在蚀刻过程中，可以用牺牲氧化物或仅部分去除LOCOS掩模来保护衬底上的有源区域。

公开(公告)号：US6004868A

公开(公告)日：1999-12-21

申请号：US587403

申请日：1996-01-17

申请人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

发明人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

IPC分类号： H01L21/225 ,  H01L21/8238 ,  H01L21/324

CPC分类号： H01L21/823892 ,  H01L21/2253

摘要： Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

公开(公告)号：US06509250B2

公开(公告)日：2003-01-21

申请号：US09991105

申请日：2001-11-21

申请人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

发明人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

IPC分类号： H01L21324

CPC分类号： H01L21/823892 ,  H01L21/2253

摘要： Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

公开(公告)号：US08451650B2

公开(公告)日：2013-05-28

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： G11C11/24

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US08374037B2

公开(公告)日：2013-02-12

申请号：US13186796

申请日：2011-07-20

申请人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

发明人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

IPC分类号： G11C16/10

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

摘要翻译： 半导体磁存储器件具有形成在存储单元上的磁性隧道结。 存储单元具有由浮动栅极包围的控制门。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

公开(公告)号：US20120258577A1

公开(公告)日：2012-10-11

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： H01L21/8239

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。