公开(公告)号：US20060267207A1

公开(公告)日：2006-11-30

申请号：US11347053

申请日：2006-02-03

申请人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

发明人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76847 ,  H01L21/76873

摘要： In a method of forming a semiconductor structure, an opening is formed in a layer of a dielectric material provided over an electrically conductive feature. An etching process is performed in order to form a recess in the electrically conductive feature. The bottom of the recess may have a rounded shape. The recess and the opening are filled with an electrically conductive material. Due to the provision of the recess, electromigration, stress migration and a local heating of the semiconductor structure, which may adversely affect the functionality of the semiconductor structure, can be reduced.

摘要翻译： 在形成半导体结构的方法中，在设置在导电特征上的介电材料层中形成开口。 执行蚀刻处理以在导电特征中形成凹部。 凹部的底部可以具有圆形形状。 凹部和开口填充有导电材料。 由于设置凹部，可以减少可能不利地影响半导体结构的功能的电迁移，应力迁移和半导体结构的局部加热。

公开(公告)号：US20060267201A1

公开(公告)日：2006-11-30

申请号：US11295756

申请日：2005-12-07

申请人： Peter Huebler ,  Frank Koschinsky ,  Frank Feustel

发明人： Peter Huebler ,  Frank Koschinsky ,  Frank Feustel

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing a stiffening layer at three sidewalls of a trench to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material may be compensated for, at least to a certain degree, thereby reducing electromigration effects and hence increasing lifetime of sophisticated semiconductor devices having metallization layers including low-k dielectric materials in combination with copper-based metal lines.

摘要翻译： 通过在要填充含铜金属的沟槽的三个侧壁处设置加强层，可以至少在一定程度上补偿低k材料的减少的热机械约束，从而降低电迁移效应并因此增加 具有包括低k电介质材料与铜基金属线组合的金属化层的复杂半导体器件的寿命。

公开(公告)号：US07063091B2

公开(公告)日：2006-06-20

申请号：US11072139

申请日：2005-03-04

申请人： Frank Koschinsky ,  Volker Kahlert ,  Peter Huebler

发明人： Frank Koschinsky ,  Volker Kahlert ,  Peter Huebler

IPC分类号： H01L21/302 ,  B08B6/00

CPC分类号： H01L21/02063 ,  H01L21/76814

摘要： A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

摘要翻译： 公开了用于清洁基底表面的清洁方法，其中所述表面包括介电材料的部分和导电材料的部分。 根据所公开的方法，在实际的清洁步骤中，在诸如氩气环境的反应性和/或惰性等离子体环境中，将衬底表面处的温度保持在预定值以下，其中预定值对应于表面 发生导电材料附聚的温度。

公开(公告)号：US20050230344A1

公开(公告)日：2005-10-20

申请号：US11072139

申请日：2005-03-04

申请人： Frank Koschinsky ,  Volker Kahlert ,  Peter Huebler

发明人： Frank Koschinsky ,  Volker Kahlert ,  Peter Huebler

IPC分类号： H01L21/02 ,  H01L21/283 ,  H01L21/302 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/76814

摘要： A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

摘要翻译： 公开了用于清洁基底表面的清洁方法，其中所述表面包括介电材料的部分和导电材料的部分。 根据所公开的方法，在实际的清洁步骤中，在诸如氩气环境的反应性和/或惰性等离子体环境中，将衬底表面处的温度保持在预定值以下，其中预定值对应于表面 发生导电材料附聚的温度。

公开(公告)号：US20050242435A1

公开(公告)日：2005-11-03

申请号：US11046986

申请日：2005-01-31

申请人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

发明人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

IPC分类号： H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

摘要翻译： 将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。 因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

公开(公告)号：US08698312B2

公开(公告)日：2014-04-15

申请号：US11046986

申请日：2005-01-31

申请人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

发明人： James Werking ,  Frank Feustel ,  Christian Zistl ,  Peter Huebler

IPC分类号： H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

摘要翻译： 将诸如二氧化硅或氟掺杂二氧化硅的增强的机械稳定性的介电材料引入到低k互连结构的通孔水平中，特别是在器件的封装期间提供了更高的总体机械稳定性。 因此，即使使用有机封装基板，在高端低k互连结构中经常观察到的裂纹和分层也可能显着降低。

公开(公告)号：US20090218629A1

公开(公告)日：2009-09-03

申请号：US12260147

申请日：2008-10-29

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

IPC分类号： H01L47/00 ,  H01L21/31

CPC分类号： H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

摘要： In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.

摘要翻译： 在双重应力衬垫方法中，可以基于等离子体辅助氧化工艺而不是通过沉积来提供中间蚀刻停止材料，从而减小蚀刻停止材料的对应厚度。 因此，与常规策略相比，所产生的纵横比可能不太明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件。

公开(公告)号：US08039395B2

公开(公告)日：2011-10-18

申请号：US11009575

申请日：2004-12-10

申请人： Moritz-Andreas Meyer ,  Hans-Juergen Engelmann ,  Ehrenfried Zschech ,  Peter Huebler

发明人： Moritz-Andreas Meyer ,  Hans-Juergen Engelmann ,  Ehrenfried Zschech ,  Peter Huebler

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.

摘要翻译： 在形成铜线之前，例如通过将掺杂剂材料结合到阻挡层中，然后通过热处理将其驱动到弱界面附近，沉积合金形成掺杂剂材料。 如通过相应的研究所示，掺杂剂材料通过晶界区域而不是通过本体铜材料（铜颗粒）基本上传递到弱界面，从而在界面附近实现适度高的合金浓度，同时保持相对较低的总体 颗粒内浓度 界面处的合金减少沿界面的电迁移。

公开(公告)号：US07416992B2

公开(公告)日：2008-08-26

申请号：US11287632

申请日：2005-11-28

申请人： Matthias Lehr ,  Peter Huebler ,  Christian Zistl

发明人： Matthias Lehr ,  Peter Huebler ,  Christian Zistl

IPC分类号： H01L21/44 ,  H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/3146 ,  H01L21/76808 ,  H01L21/7681 ,  Y10S438/952

摘要： By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.

摘要翻译： 通过使用用于构图先进半导体器件的低k电介质材料的非金属硬掩模，获得了更高程度的蚀刻保真度。 本发明可以容易地应用于通过第一沟槽最后沟槽第一通孔最后方案。

公开(公告)号：US07183629B2

公开(公告)日：2007-02-27

申请号：US10813223

申请日：2004-03-30

申请人： Hans-Juergen Engelmann ,  Ehrenfried Zschech ,  Peter Huebler

发明人： Hans-Juergen Engelmann ,  Ehrenfried Zschech ,  Peter Huebler

IPC分类号： H01L21/4763

CPC分类号： H01L21/76888 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.

摘要翻译： 在形成半导体器件的金属化层期间，在金属线的上方形成覆盖层，随后进行注入工艺，以便改变覆盖层和金属线之间的界面附近的金属。 因此，可以获得金属线的电迁移的改进的行为，从而提高器件的可靠性。