Method of forming electrically conductive lines in an integrated circuit
    1.
    发明申请
    Method of forming electrically conductive lines in an integrated circuit 审中-公开
    在集成电路中形成导电线的方法

    公开(公告)号:US20060267207A1

    公开(公告)日:2006-11-30

    申请号:US11347053

    申请日:2006-02-03

    IPC分类号: H01L23/48 H01L21/4763

    摘要: In a method of forming a semiconductor structure, an opening is formed in a layer of a dielectric material provided over an electrically conductive feature. An etching process is performed in order to form a recess in the electrically conductive feature. The bottom of the recess may have a rounded shape. The recess and the opening are filled with an electrically conductive material. Due to the provision of the recess, electromigration, stress migration and a local heating of the semiconductor structure, which may adversely affect the functionality of the semiconductor structure, can be reduced.

    摘要翻译: 在形成半导体结构的方法中,在设置在导电特征上的介电材料层中形成开口。 执行蚀刻处理以在导电特征中形成凹部。 凹部的底部可以具有圆形形状。 凹部和开口填充有导电材料。 由于设置凹部,可以减少可能不利地影响半导体结构的功能的电迁移,应力迁移和半导体结构的局部加热。

    Method for cleaning the surface of a substrate
    3.
    发明申请
    Method for cleaning the surface of a substrate 有权
    洗涤基材表面的方法

    公开(公告)号:US20050230344A1

    公开(公告)日:2005-10-20

    申请号:US11072139

    申请日:2005-03-04

    CPC分类号: H01L21/02063 H01L21/76814

    摘要: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

    摘要翻译: 公开了用于清洁基底表面的清洁方法,其中所述表面包括介电材料的部分和导电材料的部分。 根据所公开的方法,在实际的清洁步骤中,在诸如氩气环境的反应性和/或惰性等离子体环境中,将衬底表面处的温度保持在预定值以下,其中预定值对应于表面 发生导电材料附聚的温度。

    Method for cleaning the surface of a substrate
    4.
    发明授权
    Method for cleaning the surface of a substrate 有权
    洗涤基材表面的方法

    公开(公告)号:US07063091B2

    公开(公告)日:2006-06-20

    申请号:US11072139

    申请日:2005-03-04

    IPC分类号: H01L21/302 B08B6/00

    CPC分类号: H01L21/02063 H01L21/76814

    摘要: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

    摘要翻译: 公开了用于清洁基底表面的清洁方法,其中所述表面包括介电材料的部分和导电材料的部分。 根据所公开的方法,在实际的清洁步骤中,在诸如氩气环境的反应性和/或惰性等离子体环境中,将衬底表面处的温度保持在预定值以下,其中预定值对应于表面 发生导电材料附聚的温度。

    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices
    5.
    发明授权
    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices 有权
    减少半导体器件金属化系统种子层损伤的试验系统和方法

    公开(公告)号:US08323989B2

    公开(公告)日:2012-12-04

    申请号:US12749805

    申请日:2010-03-30

    IPC分类号: H01L21/66 H01L23/58

    摘要: During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译: 在形成复杂的金属化系统期间,可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如,可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理,从而能够有效评估环境的一个或多个参数。 此外,可以基于本文公开的测试策略获得优化的制造环境。

    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    6.
    发明申请
    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 有权
    在半导体器件金属化系统中减少种植层损伤的测试系统和方法

    公开(公告)号:US20100244028A1

    公开(公告)日:2010-09-30

    申请号:US12749805

    申请日:2010-03-30

    IPC分类号: H01L21/768 H01L23/544

    摘要: During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译: 在形成复杂的金属化系统期间,可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如,可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理,从而能够有效评估环境的一个或多个参数。 此外,可以基于本文公开的测试策略获得“优化的”制造环境。

    Method of testing an integrity of a material layer in a semiconductor structure
    7.
    发明授权
    Method of testing an integrity of a material layer in a semiconductor structure 有权
    测试半导体结构中的材料层的完整性的方法

    公开(公告)号:US08058081B2

    公开(公告)日:2011-11-15

    申请号:US11777355

    申请日:2007-07-13

    IPC分类号: H01L21/66

    CPC分类号: H01L21/76868 H01L22/12

    摘要: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

    摘要翻译: 一种方法包括提供半导体结构。 该半导体结构包括一特征,该特征包括形成在该特征上的第一材料和第二材料层。 半导体结构暴露于蚀刻剂。 蚀刻剂适于选择性地去除第一材料,使第二材料基本上保持不变。 在将半导体结构暴露于蚀刻剂之后,检测特征是否受蚀刻剂的影响。

    Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition
    8.
    发明授权
    Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition 有权
    通过在阻挡层沉积期间进行沉积/蚀刻循环,在BEOL处理期间减少半导体衬底的污染

    公开(公告)号:US08039400B2

    公开(公告)日:2011-10-18

    申请号:US12418857

    申请日:2009-04-06

    IPC分类号: H01L21/302

    摘要: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

    摘要翻译: 可以基于一个或多个沉积/蚀刻循环形成半导体器件的金属化系统的导电阻挡材料,从而在斜面区域中提供减小的材料厚度,同时增强半导体的有源区域中的总厚度均匀性 基质。 在一些说明性实施例中,可以使用两个或更多个沉积/蚀刻循环,从而提供为模具区域中的阻挡层厚度选择减小的目标值的可能性,同时在斜面区域中也获得显着减小的厚度。

    MULTI-STEP DEPOSITION CONTROL
    9.
    发明申请
    MULTI-STEP DEPOSITION CONTROL 有权
    多步沉积控制

    公开(公告)号:US20080299681A1

    公开(公告)日:2008-12-04

    申请号:US12021791

    申请日:2008-01-29

    IPC分类号: H01L21/66 B05C11/00

    摘要: For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters.

    摘要翻译: 为了提供两步或多步沉积过程的控制,提供了一种方法和相应的沉积系统,其包括提供具有采用不同工艺参数集的至少两个子过程的沉积工艺,其中每组工艺参数包括 至少一个过程参数。 该方法包括通过考虑到相应的第一过程参数的至少一个先前值来可控地生成至少一个第一过程参数的实际值,其中每个第一过程参数是所述至少两组过程参数的过程参数。

    Methods of forming metal nitride materials
    10.
    发明授权
    Methods of forming metal nitride materials 有权
    形成金属氮化物材料的方法

    公开(公告)号:US09177826B2

    公开(公告)日:2015-11-03

    申请号:US13364671

    申请日:2012-02-02

    摘要: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

    摘要翻译: 本文公开了在各种类型的半导体器件上形成金属氮化物层的各种方法。 在一个示例中,该方法包括在半导体衬底上形成绝缘材料层,执行物理气相沉积工艺以在绝缘材料层之上形成金属氮化物层,其中金属氮化物层具有本征沉积的应力水平 并且对金属氮化物层进行至少一个处理操作以减少金属氮化物层中本征沉积应力水平的大小。