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119 条记录 (耗时 0.028 秒)

    Method of forming electrically conductive lines in an integrated circuit
    1.
    发明申请
    Method of forming electrically conductive lines in an integrated circuit 审中-公开
    在集成电路中形成导电线的方法

    公开(公告)号：US20060267207A1

    公开(公告)日：2006-11-30

    申请号：US11347053

    申请日：2006-02-03

    申请人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

    发明人： Frank Feustel ,  Frank Koschinsky ,  Peter Huebler

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76807 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76847 ,  H01L21/76873

    摘要： In a method of forming a semiconductor structure, an opening is formed in a layer of a dielectric material provided over an electrically conductive feature. An etching process is performed in order to form a recess in the electrically conductive feature. The bottom of the recess may have a rounded shape. The recess and the opening are filled with an electrically conductive material. Due to the provision of the recess, electromigration, stress migration and a local heating of the semiconductor structure, which may adversely affect the functionality of the semiconductor structure, can be reduced.

    摘要翻译： 在形成半导体结构的方法中，在设置在导电特征上的介电材料层中形成开口。 执行蚀刻处理以在导电特征中形成凹部。 凹部的底部可以具有圆形形状。 凹部和开口填充有导电材料。 由于设置凹部，可以减少可能不利地影响半导体结构的功能的电迁移，应力迁移和半导体结构的局部加热。

    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    3.
    发明申请
    TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 有权
    在半导体器件金属化系统中减少种植层损伤的测试系统和方法

    公开(公告)号：US20100244028A1

    公开(公告)日：2010-09-30

    申请号：US12749805

    申请日：2010-03-30

    申请人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    发明人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    IPC分类号： H01L21/768 ,  H01L23/544

    CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译： 在形成复杂的金属化系统期间，可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如，可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理，从而能够有效评估环境的一个或多个参数。 此外，可以基于本文公开的测试策略获得“优化的”制造环境。

    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices
    4.
    发明授权
    Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices 有权
    减少半导体器件金属化系统种子层损伤的试验系统和方法

    公开(公告)号：US08323989B2

    公开(公告)日：2012-12-04

    申请号：US12749805

    申请日：2010-03-30

    申请人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    发明人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

    IPC分类号： H01L21/66 ,  H01L23/58

    CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

    摘要翻译： 在形成复杂的金属化系统期间，可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如，可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理，从而能够有效评估环境的一个或多个参数。 此外，可以基于本文公开的测试策略获得优化的制造环境。

    Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions
    8.
    发明授权
    Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions 有权
    半导体器件包括自对准接触棒和具有增加的通过着陆区域的金属线

    公开(公告)号：US08399352B2

    公开(公告)日：2013-03-19

    申请号：US13331606

    申请日：2011-12-20

    申请人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    发明人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.

    摘要翻译： 当形成金属零电平的金属线时，可以通过使用适当的图案化方案来实现减小的底部宽度和增加的顶部宽度，例如在形成具有顶部宽度的上部沟槽部分之后使用间隔结构，或者形成下部 并且随后应用进一步实现顶部宽度的掩模和蚀刻方案。 以这种方式，可以提供连接到自对准接触棒的金属线，以便表现出20nm以下的底部宽度，而顶部宽度可以允许与金属化系统的任何通孔的可靠接触。

    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER
    10.
    发明申请
    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER 审中-公开
    采用拉伸应力覆盖层的替代浇口方法中的超级填充条件

    公开(公告)号：US20120223388A1

    公开(公告)日：2012-09-06

    申请号：US13471818

    申请日：2012-05-15

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823807 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7843

    摘要： In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

    摘要翻译： 在用于在半导体器件中形成高k金属栅电极的替代栅极方法中，栅极开口的锥形配置可以通过使用横向邻近栅电极结构设置的拉应力电介质材料来实现。 因此，可以实现优异的沉积条件，同时可以有效地将拉伸应力分量用于一种类型的晶体管中的应变工程。 此外，可以在提供替换栅电极结构之后施加附加的压缩应力介电材料。