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1.发明申请Technique for forming embedded metal lines having increased resistance against stress-induced material transport 有权用于形成具有增加的抗应力诱导材料输送阻力的嵌入式金属线的技术公开(公告)号：US20050161817A1
公开(公告)日：2005-07-28
申请号：US11009575
申请日：2004-12-10
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.
摘要翻译： 在形成铜线之前，例如通过将掺杂剂材料结合到阻挡层中，然后通过热处理将其驱动到弱界面附近，沉积合金形成掺杂剂材料。 如通过相应的研究所示，掺杂剂材料通过晶界区域而不是通过本体铜材料（铜晶粒）基本上传递到弱界面，从而在界面附近实现适度高的合金浓度，同时保持相对较低的总体 颗粒内浓度 界面处的合金减少沿界面的电迁移。
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2.发明授权Technique for forming embedded metal lines having increased resistance against stress-induced material transport 有权用于形成具有增加的抗应力诱导材料输送阻力的嵌入式金属线的技术公开(公告)号：US08039395B2
公开(公告)日：2011-10-18
申请号：US11009575
申请日：2004-12-10
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.
摘要翻译： 在形成铜线之前，例如通过将掺杂剂材料结合到阻挡层中，然后通过热处理将其驱动到弱界面附近，沉积合金形成掺杂剂材料。 如通过相应的研究所示，掺杂剂材料通过晶界区域而不是通过本体铜材料（铜颗粒）基本上传递到弱界面，从而在界面附近实现适度高的合金浓度，同时保持相对较低的总体 颗粒内浓度 界面处的合金减少沿界面的电迁移。
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3.发明申请Metal line having an increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line 有权金属线通过将材料注入金属线中而沿着介电阻挡层的界面具有增加的电迁移阻力公开(公告)号：US20050046031A1
公开(公告)日：2005-03-03
申请号：US10813223
申请日：2004-03-30
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L23/48
CPC分类号： H01L21/76888 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.
摘要翻译： 在形成半导体器件的金属化层期间，在金属线的上方形成覆盖层，随后进行注入工艺，以便改变覆盖层和金属线之间的界面附近的金属。 因此，可以获得金属线的电迁移的改进的行为，从而提高器件的可靠性。
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4.发明授权Metal line having an increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line 有权金属线通过将材料注入金属线中而沿着介电阻挡层的界面具有增加的电迁移阻力公开(公告)号：US07183629B2
公开(公告)日：2007-02-27
申请号：US10813223
申请日：2004-03-30
IPC分类号： H01L21/4763
CPC分类号： H01L21/76888 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.
摘要翻译： 在形成半导体器件的金属化层期间，在金属线的上方形成覆盖层，随后进行注入工艺，以便改变覆盖层和金属线之间的界面附近的金属。 因此，可以获得金属线的电迁移的改进的行为，从而提高器件的可靠性。
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公开(公告)号：US06303399B1
公开(公告)日：2001-10-16
申请号：US09800441
申请日：2001-03-06
IPC分类号： H01L2166
CPC分类号： G01N1/2806 , G01R31/307
摘要： A method is provided for preparing a sample for cross-section analysis by a transmission electron microscope. Semiconductor samples containing recessed portions or unfilled structures are filled with a filling material so as to produce a planar top surface onto which a metal layer can be deposited for thinning the sample to a thickness of less than 100 nm by an FIB technique.
摘要翻译： 提供了一种通过透射电子显微镜制备用于横截面分析的样品的方法。 包含凹部或未填充结构的半导体样品填充有填充材料，以便产生平面顶表面，通过FIB技术，可以沉积金属层以使样品变薄至小于100nm的厚度。
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公开(公告)号：US06953755B2
公开(公告)日：2005-10-11
申请号：US10677911
申请日：2003-10-02
IPC分类号： G01N23/04 , G01N23/223 , G01R31/28 , H01L21/44
CPC分类号： G01N23/04 , G01N23/223 , G01N2223/076
摘要： By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored. Moreover, displaying some of the measurement results as a quick motion representation enables the detection of subtle changes of characteristics of an interconnect structure in a highly efficient manner.
摘要翻译： 通过准备通过电子显微镜或X射线显微镜进行横截面分析的完全嵌入的互连结构样品，可以有效地监测降解机理。 此外，将一些测量结果显示为快速运动表示能够以高效的方式检测互连结构的特征的微妙变化。
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7.发明申请INSULATION MATERIAL FOR INTEGRATED CIRCUITS AND USE OF SAID INTEGRATED CIRCUITS 有权用于集成电路的绝缘材料和集成电路的使用公开(公告)号：US20110297869A1
公开(公告)日：2011-12-08
申请号：US13202228
申请日：2010-02-03
CPC分类号： H01L21/02118 , H01L21/02175 , H01L21/312
摘要： The invention relates to the fields of microelectronics and materials sciences and concerns an insulation layer material for integrated circuits in microelectronics, which can be used, for example, in integrated circuits as insulation material in semiconductor components. The object of the present invention is to disclose an insulation material for integrated circuits, which has dielectric constants of k≦2 with good mechanical properties at the same time. The object is attained with an insulation material for integrated circuits, containing at least MOFs and/or COFs.
摘要翻译： 本发明涉及微电子学和材料科学领域，涉及用于微电子学集成电路的绝缘层材料，其可以用作例如集成电路作为半导体部件中的绝缘材料。 本发明的目的是公开具有同时具有良好机械性能的介电常数k＆nlE; 2的用于集成电路的绝缘材料。 该目的是用于至少包含MOF和/或COF的用于集成电路的绝缘材料。
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公开(公告)号：US20050072919A1
公开(公告)日：2005-04-07
申请号：US10677911
申请日：2003-10-02
申请人： Moritz Meyer , Ehrenfried Zschech , Eckhard Langer
发明人： Moritz Meyer , Ehrenfried Zschech , Eckhard Langer
IPC分类号： G01N23/04 , G01N23/223 , G01N23/00
CPC分类号： G01N23/04 , G01N23/223 , G01N2223/076
摘要： By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored. Moreover, displaying some of the measurement results as a quick motion representation enables the detection of subtle changes of characteristics of an interconnect structure in a highly efficient manner.
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9.发明授权Nanoprobe tip for advanced scanning probe microscopy comprising a layered probe material patterned by lithography and/or FIB techniques 失效用于高级扫描探针显微镜的纳米针尖，包括通过光刻和/或FIB技术图案化的分层探针材料公开(公告)号：US08056402B2
公开(公告)日：2011-11-15
申请号：US12114121
申请日：2008-05-02
IPC分类号： G01B5/28
CPC分类号： G01Q70/14
摘要： By forming an appropriate material layer, such as a metal-containing material, on a appropriate substrate and patterning the material layer to obtain a cantilever portion and a tip portion, a specifically designed nano-probe may be provided. In some illustrative aspects, additionally, a three-dimensional template structure may be provided prior to the deposition of the probe material, thereby enabling the definition of sophisticated tip portions on the basis of lithography, wherein, alternatively or additionally, other material removal processes with high spatial resolution, such as FIB techniques, may be used for defining nano-probes, which may be used for electric interaction, highly resolved temperature measurements and the like. Thus, sophisticated measurement techniques may be established for advanced thermal scanning, strain measurement techniques and the like, in which a thermal and/or electrical interaction with the surface under consideration is required. These techniques may be advantageously used for failure localization and local analysis during the fabrication of advanced integrated circuits.
摘要翻译： 通过在合适的基材上形成合适的材料层（例如含金属的材料）并图案化材料层以获得悬臂部分和尖端部分，可以提供特别设计的纳米探针。 在一些说明性方面，另外，可以在沉积探针材料之前提供三维模板结构，从而能够在光刻的基础上定义复杂的尖端部分，其中替代地或另外地，其它材料去除过程与 可以使用诸如FIB技术的高空间分辨率来定义可用于电相互作用，高度分辨的温度测量等的纳米探针。 因此，可以针对先进的热扫描，应变测量技术等建立复杂的测量技术，其中需要与所考虑的表面的热和/或电相互作用。 这些技术可有利地用于高级集成电路制造期间的故障定位和局部分析。
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10.发明授权Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure 有权包括应力敏感元件的半导体结构和测量半导体结构中的应力的方法公开(公告)号：US07311008B2
公开(公告)日：2007-12-25
申请号：US11058706
申请日：2005-02-15
申请人： Eckhard Langer , Ehrenfried Zschech
发明人： Eckhard Langer , Ehrenfried Zschech
CPC分类号： G01L5/0047 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprises a stress sensitive element. A property of the stress sensitive element is representative of a stress in the semiconductor structure. Additionally, the semiconductor structure may comprise an electrical element. The stress sensitive element and the electrical element comprise portions of a common layer structure. Analyzers may be adapted to determine a property of the stress sensitive element being representative of a stress in the semiconductor structure and a property of the electrical element. The property of the stress sensitive element may be determined and the manufacturing process may be modified based on the determined property of the stress sensitive element. The property of the electrical element may be related to the property of the stress sensitive element in order to investigate an influence of stress on the electrical element.
摘要翻译： 半导体结构包括应力敏感元件。 应力敏感元件的特性代表半导体结构中的应力。 另外，半导体结构可以包括电气元件。 应力敏感元件和电气元件包括公共层结构的部分。 分析器可以适于确定应力敏感元件的性质代表半导体结构中的应力和电元件的性质。 可以确定应力敏感元件的性质，并且可以基于确定的应力敏感元件的性质来修改制造过程。 电元件的性质可能与应力敏感元件的性质有关，以便研究应力对电气元件的影响。
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