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    High speed bus contact system
    2.
    发明授权
    High speed bus contact system 失效
    高速总线接触系统

    公开(公告)号：US06322370B1

    公开(公告)日：2001-11-27

    申请号：US09061807

    申请日：1998-04-16

    申请人： Frank P. Hart ,  Raviprakash Nagaraj ,  Leonard O. Turner ,  Arthur L. Spurrell

    发明人： Frank P. Hart ,  Raviprakash Nagaraj ,  Leonard O. Turner ,  Arthur L. Spurrell

    IPC分类号： H01R13648

    CPC分类号： H01R12/83 ,  H01R13/658

    摘要： The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

    摘要翻译： 本发明是用于容纳与主板平行的存储模块的存储总线连接器。 本发明的存储器总线连接器具有多个单独的触点，其作为数据信号触点和/或接地部件，其连接到并行存储器模块的下部。 本发明的存储器总线连接器还具有连接到存储器模块的上部的片状接地部件。

    Mechanism for automatically enabling and disabling clock signals
    4.
    发明授权
    Mechanism for automatically enabling and disabling clock signals 失效
    自动启用和禁用时钟信号的机制

    公开(公告)号：US5754069A

    公开(公告)日：1998-05-19

    申请号：US644178

    申请日：1996-05-10

    申请人： Raviprakash Nagaraj

    发明人： Raviprakash Nagaraj

    IPC分类号： G06F1/04 ,  H03K17/22 ,  G06F1/10 ,  H03K17/28

    CPC分类号： G06F1/04

    摘要： A mechanism for automatically enabling and disabling clock signals includes a driver for providing a clock signal as an output, a gate coupled to the driver, and a sensing circuit coupled to both the output of the driver and to the gate. The sensing circuit provides a signal to the gate responsive to the output being in a first state. The gate then prevents the driver from driving the clock signal responsive to the signal from the sensing circuit. In one embodiment, a generator is coupled to the driver for providing a waveform to the driver. The driver then provides the clock signal based on this input waveform. Additionally, the gate is situated between the generator and the driver. The gate, based on the output of the sensing circuit, can then prevent the waveform from being provided to the driver.

    摘要翻译： 用于自动启用和禁用时钟信号的机构包括用于提供作为输出的时钟信号的驱动器，耦合到驱动器的栅极和耦合到驱动器的输出和门的感测电路。 感测电路根据输出处于第一状态向门提供信号。 然后，门防止驱动器响应于来自感测电路的信号来驱动时钟信号。 在一个实施例中，发电机耦合到驱动器以向驱动器提供波形。 然后，驱动器根据该输入波形提供时钟信号。 另外，门位于发电机和驱动器之间。 基于感测电路的输出的门可以防止向驱动器提供波形。

    VIRTUAL POINT OF SALE
    5.
    发明申请
    VIRTUAL POINT OF SALE 审中-公开
    虚拟销售点

    公开(公告)号：US20140074635A1

    公开(公告)日：2014-03-13

    申请号：US13976166

    申请日：2011-12-29

    申请人： Kenneth W. Reese ,  Raviprakash Nagaraj

    发明人： Kenneth W. Reese ,  Raviprakash Nagaraj

    IPC分类号： G06Q20/20 ,  G06Q20/38 ,  G06Q20/40

    CPC分类号： G06Q20/202 ,  G06Q20/20 ,  G06Q20/206 ,  G06Q20/3278 ,  G06Q20/3821 ,  G06Q20/401 ,  G06Q20/4014

    摘要： In one embodiment a controller comprises logic to receive a payment request for a purchase transaction, wherein the payment request comprises transaction information associated with the purchase transaction, present at least a portion of the transaction information on a user interface, receive payment source data from a remote resource, securely wrap the payment source data and transmit the payment source data to a remote device. Other embodiments may be described.

    摘要翻译： 在一个实施例中，控制器包括接收购买交易的支付请求的逻辑，其中支付请求包括与购买交易相关联的交易信息，在用户界面上呈现交易信息的至少一部分，从 远程资源，安全地包裹支付源数据并将支付源数据传送到远程设备。 可以描述其他实施例。

    Low power optimized voltage regulator
    7.
    发明授权
    Low power optimized voltage regulator 失效
    低功耗优化电压调节器

    公开(公告)号：US07679340B2

    公开(公告)日：2010-03-16

    申请号：US11823973

    申请日：2007-06-29

    申请人： Krishnan Ravichandran ,  Raviprakash Nagaraj

    发明人： Krishnan Ravichandran ,  Raviprakash Nagaraj

    IPC分类号： G05F3/16

    CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

    摘要： Methods and apparatus relating to low power optimized voltage regulators are described. In one embodiment, a voltage regulator controller may cause leakage current from a load to drain a capacitor (e.g., coupled in parallel with the load) during a reduced power state.

    摘要翻译： 描述与低功率优化电压调节器有关的方法和设备。 在一个实施例中，电压调节器控制器可以在降低的功率状态期间引起来自负载的漏电流以排出电容器（例如，与负载并联耦合）。

    ENHANCED WIRELESS COMMUNICATION SECURITY
    9.
    发明申请
    ENHANCED WIRELESS COMMUNICATION SECURITY 有权
    增强无线通信安全

    公开(公告)号：US20140169560A1

    公开(公告)日：2014-06-19

    申请号：US13715611

    申请日：2012-12-14

    申请人： Reinhard STOTZER ,  Kenneth Reese ,  Raviprakash Nagaraj

    发明人： Reinhard STOTZER ,  Kenneth Reese ,  Raviprakash Nagaraj

    IPC分类号： H04W12/00

    CPC分类号： H04W12/02 ,  H04W12/04 ,  H04W12/06 ,  H04W12/08 ,  H04W12/12 ,  H04W84/18

    摘要： Systems, methods, and devices are directed to an electronic device that includes a first wireless communication module configured to facilitate transmission and reception of data via a wireless communication link and a first secure element while a wireless communication device includes a processor, an operating system executed by the processor, a second wireless communication module configured to facilitate transmission and reception of data via the wireless communication link, and a second secure element. The second secure element exchanges information with the first secure element via the wireless communication link to establish a secure channel within the wireless communication link, and the wireless communication device employs logic configured to route the data to the second secure element for processing prior to forwarding the data to the operating system, upon establishing the secure channel.

    摘要翻译： 系统，方法和设备涉及电子设备，其包括第一无线通信模块，其被配置为便于在无线通信设备包括处理器的同时通过无线通信链路和第一安全元件传输和接收数据，执行的操作系统 通过处理器，第二无线通信模块被配置为便于通过无线通信链路传输和接收数据，以及第二安全元件。 所述第二安全元件经由所述无线通信链路与所述第一安全元件交换信息，以在所述无线通信链路内建立安全通道，并且所述无线通信设备使用被配置为将数据路由到所述第二安全元件以进行处理的逻辑， 建立安全通道后，向操作系统提供数据。

    GRADIENT NON-LINEAR ADAPTIVE POWER ARCHITECTURE AND SCHEME
    10.
    发明申请
    GRADIENT NON-LINEAR ADAPTIVE POWER ARCHITECTURE AND SCHEME 审中-公开
    梯度非线性自适应功率结构和方案

    公开(公告)号：US20070248877A1

    公开(公告)日：2007-10-25

    申请号：US11691331

    申请日：2007-03-26

    申请人： Jaber Qahoug ,  Lilly Huang ,  Raviprakash Nagaraj

    发明人： Jaber Qahoug ,  Lilly Huang ,  Raviprakash Nagaraj

    IPC分类号： H01M2/00 ,  G05F5/00

    CPC分类号： H02J1/10 ,  H02J3/46

    摘要： Techniques related to a power module employing multiple power sub-modules are described. More specifically, an embodiment combines and controls multiple power sub-modules of varying characteristics to improve the overall efficiency of the power module across varying load currents, power outputs, input voltages, and other operating conditions. Moreover, the power module may employ an adaptive non-linear and non-uniform current/power sharing among its power sub-modules. Other embodiments are described and claimed.

    摘要翻译： 描述了与使用多个功率子模块的功率模块有关的技术。 更具体地，实施例组合并控制具有不同特性的多个功率子模块，以改善功率模块在不同的负载电流，功率输出，输入电压和其它工作条件下的整体效率。 此外，功率模块可以在其功率子模块之间采用自适应非线性和非均匀的电流/功率共享。 描述和要求保护其他实施例。