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    DRAM memory cell
    1.
    发明授权
    DRAM memory cell 失效
    DRAM存储单元

    公开(公告)号：US07368752B2

    公开(公告)日：2008-05-06

    申请号：US10839800

    申请日：2004-05-06

    申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

    CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

    摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

    摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08097915B2

    公开(公告)日：2012-01-17

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    发明人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    IPC分类号： H01L31/119

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
    9.
    发明申请
    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US20090309152A1

    公开(公告)日：2009-12-17

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

    Integrated circuits having a contact region and methods for manufacturing the same
    10.
    发明授权
    Integrated circuits having a contact region and methods for manufacturing the same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US07915667B2

    公开(公告)日：2011-03-29

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。