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1.发明授权Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 失效使用N沟道栅极的选择性掺杂和激活来制造N沟道和P沟道IGFET的方法
公开(公告)号：US6051459A
公开(公告)日：2000-04-18
申请号：US803730
申请日：1997-02-21
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.
摘要翻译： 公开了制造N沟道和P沟道IGFET的方法。 该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括 在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分 栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂 在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层， 在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极 并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。 有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。
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公开(公告)号：US6069398A
公开(公告)日：2000-05-30
申请号：US905306
申请日：1997-08-01
CPC分类号： H01L28/20 , H01L27/0688
摘要： A resistor is formed between devices in an integrated circuit by forming a patterned trench in an intralayer dielectric (ILD) deposited over the devices, filling the trench with polysilicon and planarizing the polysilicon. The resistance of the resistor is defined by determining and selecting the size and form of the trench including the width, length, depth and orientation of the trench. In some embodiments, the resistance of the resistor is also controlled by adding selected amounts and species of dopants to the polysilicon. In some embodiments, the resistance is controlled by directly saliciding the polysilicon in the trench.
摘要翻译： 通过在沉积在器件上的层间电介质（ILD）中形成图案化沟槽，用多晶硅填充沟槽并平坦化多晶硅，在集成电路中的器件之间形成电阻器。 通过确定和选择包括沟槽的宽度，长度，深度和取向的沟槽的尺寸和形式来限定电阻器的电阻。 在一些实施例中，电阻器的电阻也通过将选定量和种类的掺杂剂添加到多晶硅来控制。 在一些实施例中，通过在沟槽中直接浇注多晶硅来控制电阻。
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3.发明授权Method of forming a contact hole in an interlevel dielectric layer using dual etch stops 失效使用双蚀刻停止在层间电介质层中形成接触孔的方法
公开(公告)号：US5912188A
公开(公告)日：1999-06-15
申请号：US905686
申请日：1997-08-04
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76832 , H01L21/31116 , H01L21/76802 , H01L21/76814 , H01L21/76834 , H01L21/76895
摘要： A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.
摘要翻译： 使用双蚀刻停止件在层间电介质层中形成接触孔的方法包括以下步骤：提供半导体衬底，在衬底上形成栅极，在衬底中形成源极/漏极区域，提供源/漏接触电耦合 形成层间电介质层，该层间介质层包括在源极/漏极接触之上的第一，第二和第三电介质层，在层间电介质层上形成蚀刻掩模，施加第一蚀刻，第一蚀刻对第一电介质具有高选择性 通过使用第二介电层作为蚀刻停止层，通过蚀刻掩模中的开口相对于第二介电层的层，从而在第一介电层中形成第一孔，该第一孔延伸到第二介电层而不延伸到第三介电层， 施加相对于第三介电层通过开口而对第二电介质层具有高度选择性的第二蚀刻 在蚀刻掩模中使用第三介电层作为蚀刻停止层，从而在第二介电层中形成延伸到第三介电层而不延伸到源极/漏极接触的第二孔，并施加高度选择性的第三蚀刻 相对于通过蚀刻掩模中的开口的源极/漏极接触的第三电介质层，从而在延伸到源极/漏极接触的第三电介质层中形成第三孔，其中组合的第一，第二和第三孔 提供接触孔。 以这种方式，接触孔形成在层间电介质中，而没有任何明显的底层材料的气刨。
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4.发明授权Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译： 复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。 下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。 第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。 通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层 ，并通过原位沉积氮掺杂的第一多晶硅层。 完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。 此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。 本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。
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5.发明授权Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion 失效晶体管源极/漏极区域之下的氮衬垫以延迟掺杂剂扩散公开(公告)号：US06225151B1
公开(公告)日：2001-05-01
申请号：US08871469
申请日：1997-06-09
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2122
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28176 , H01L21/28202 , H01L21/823814 , H01L29/1033 , H01L29/518 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7833
摘要： A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.
摘要翻译： 基本上在IGFET的源极/漏极区域下方大致相邻地形成的氮注入区域形成衬垫，以在随后的热处理操作（例如退火步骤）期间阻止源极/漏极掺杂剂原子的扩散。 可以在将源极/漏极掺杂剂注入较低深度之前通过将氮注入给定深度来形成氮衬垫。 也可以将氮气引入到栅电极下面的IGFET沟道区域的区域中，以阻止源极/漏极掺杂剂的随后的横向扩散。 可以使用一个或多个成角度的注入步骤来实现这种氮引入，或者可以通过使用与栅电极对准的垂直注入形成的注入氮层退火来实现。 衬垫可以形成在IGFET的漏极侧或源极和漏极两侧，并且可以形成在漏极和/或源极的重掺杂区域的轻掺杂区域下方。 这种衬垫对于硼掺杂的源极/漏极区域是特别有利的，并且可以与没有这样的衬垫形成的N沟道IGFET组合。
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公开(公告)号：US6005272A
公开(公告)日：1999-12-21
申请号：US28894
申请日：1998-02-24
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface. Advantageously, the source contact overlaps the trench, thereby improving packing density.
摘要翻译： 公开了具有沟槽中的栅电极和源极接触的IGFET。 IGFET包括具有相对侧壁和半导体衬底中的底表面的沟槽，底表面上的栅极绝缘体，栅极绝缘体上的栅电极，底表面上的源极接触，栅电极，源极之间的绝缘间隔 接触和侧壁，以及与底表面相邻的源极和漏极。 有利地，源极接触与沟槽重叠，从而改善了堆积密度。
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公开(公告)号：US5933721A
公开(公告)日：1999-08-03
申请号：US837580
申请日：1997-04-21
IPC分类号： H01L21/8238 , H01L21/60
CPC分类号： H01L21/823828 , H01L21/823807
摘要： A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.
摘要翻译： 公开了在具有类似导电类型的第一和第二IGFET的制造期间建立差分阈值电压的方法。 将掺杂剂引入该对的每个晶体管的栅电极。 掺杂剂差异扩散到各个沟道区域中以在其间提供差分掺杂剂浓度，这导致两个晶体管之间的差分阈值电压。 一个实施例包括在掺杂剂扩散到各个沟道区域之前将诸如氮的扩散阻滞材料引入第一栅电极中，并且不将大量的扩散阻滞材料引入第二栅电极。 有利地，单个掺杂剂注入可以提供两个阈值电压值。 可以选择两个阈值电压以提供增强模式和耗尽模式IGFET的各种组合。
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公开(公告)号：US5874341A
公开(公告)日：1999-02-23
申请号：US739567
申请日：1996-10-30
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： An IGFET with a gate electrode and a source contact in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, a source contact on the bottom surface, insulative spacers between the gate electrode, the source contact and the sidewalls, and a source and drain adjacent to the bottom surface. A method of forming an IGFET includes forming a trench with first and second opposing sidewalls and a bottom surface in a substrate, forming disposable spacers on the bottom surface, forming a gate insulator material on the bottom surface between the disposable spacers, depositing a gate electrode material on the gate insulator material and disposable spacers, polishing the gate electrode material and then anisotropically etching a lateral portion of the gate electrode material and gate insulator material to form the gate electrode and gate insulator, removing the disposable spacers, forming a first insulative spacer adjacent to the first sidewall, a second insulative spacer adjacent to the gate electrode and second sidewall, and a third insulative spacer adjacent to the gate electrode such that a contact portion of the bottom surface between the first and third insulative spacers is exposed, forming a source and drain in the substrate and adjacent to the bottom surface, and forming source and drain contacts such that the source contact is electrically coupled to the source at the contact portion of the bottom surface and the drain contact is electrically coupled to the drain at the top surface of the substrate. Advantageously, the source contact overlaps the trench, thereby improving packing density.
摘要翻译： 公开了具有沟槽中的栅电极和源极接触的IGFET。 IGFET包括具有相对侧壁和半导体衬底中的底表面的沟槽，底表面上的栅极绝缘体，栅极绝缘体上的栅电极，底表面上的源极接触，栅电极，源极之间的绝缘间隔 接触和侧壁，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括在基板中形成具有第一和第二相对侧壁和底表面的沟槽，在底表面上形成一次性间隔物，在一次性间隔物之间的底表面上形成栅极绝缘体材料，沉积栅电极 栅极绝缘体材料和一次性间隔物上的材料，抛光栅电极材料，然后各向异性地蚀刻栅极电极材料和栅极绝缘体材料的侧向部分以形成栅电极和栅极绝缘体，去除一次性间隔物，形成第一绝缘间隔物 与第一侧壁相邻的第二绝缘间隔件，与栅电极和第二侧壁相邻的第二绝缘间隔件，以及与栅电极相邻的第三绝缘间隔件，使得第一和第三绝缘间隔件之间的底表面的接触部分露出，形成 源极和漏极在衬底中并且邻近底面，并且形成 尿液和漏极接触，使得源极接触件在底表面的接触部分处电耦合到源极，并且漏极接触件电耦合到衬底顶表面处的漏极。 有利地，源极接触与沟槽重叠，从而改善了堆积密度。
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9.发明授权公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。
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10.发明授权High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure 失效高介电常数栅极电介质，其上覆盖的钽栅极导体形成在牺牲结构的侧壁表面上公开(公告)号：US06194768B1
公开(公告)日：2001-02-27
申请号：US09177867
申请日：1998-10-23
IPC分类号： H01L31119
CPC分类号： H01L29/518 , H01L21/28114 , H01L21/2815 , H01L21/823418 , H01L21/823437 , H01L29/495 , H01L29/66659
摘要： A transistor is provided having a gate conductor produced with ultra fine geometries. The gate conductor is metallic and is sized using deposition rather than photolithography. The deposition process can be closely controlled to achieve gate lengths less than a few tenths of a micron. The metallic gate conductor serves to source metal atoms during anneal of lightly doped drain regions. The metal atoms migrate to the gate dielectric directly beneath the gate conductor to convert the gate dielectric to a high K dielectric. The high K dielectric is substantially resistant to breakdown yet enjoys the benefits of high speed operation and low threshold turn-on.
摘要翻译： 提供具有以超细几何形状制造的栅极导体的晶体管。 栅极导体是金属的，其尺寸使用沉积而不是光刻。 可以严格控制沉积过程以实现小于十分之几微米的栅极长度。 金属栅极导体用于在轻掺杂漏极区退火期间引发金属原子。 金属原子迁移到栅极导体正下方的栅极电介质，将栅极电介质转换成高K电介质。 高K电介质基本上不会破坏，而且具有高速运行和低阈值开启的优点。
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