公开(公告)号：US20240233822A9

公开(公告)日：2024-07-11

申请号：US18489844

申请日：2023-10-18

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

公开(公告)号：US20240135992A1

公开(公告)日：2024-04-25

申请号：US18489844

申请日：2023-10-17

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

公开(公告)号：US11723288B2

公开(公告)日：2023-08-08

申请号：US17209107

申请日：2021-03-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N10/00 ,  H10N60/10 ,  H03K3/38 ,  H10N69/00

CPC分类号： H10N60/11 ,  G06N10/00 ,  H03K3/38 ,  H10N60/128 ,  H10N69/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US10720215B2

公开(公告)日：2020-07-21

申请号：US16246378

申请日：2019-01-11

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C11/4093 ,  G11C16/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/404

摘要： Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming. A method is provided for multiple-page programming of an array having a block that includes page groups and each page group includes cell strings that form pages. The method includes deactivating drain select gates (DSGs) and source select gates (SSG), applying a programming voltage to a selected word line, and applying a middle high voltage to unselected word lines. The method also includes repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation. Each programming operation includes loading data onto bit lines and pulsing a drain select gate associated with a selected page group to load the data into a selected page of the selected page group.

公开(公告)号：US10553293B2

公开(公告)日：2020-02-04

申请号：US16138897

申请日：2018-09-21

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/34 ,  H01L49/02 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157

摘要： A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

公开(公告)号：US20190244666A1

公开(公告)日：2019-08-08

申请号：US16265810

申请日：2019-02-01

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C14/00

CPC分类号： G11C14/0072 ,  G11C11/412 ,  G11C11/419 ,  G11C14/0081 ,  G11C14/009

摘要： Methods and apparatus for memory cells that combine static random-access memory and non-volatile memory. In an exemplary embodiment, a memory cell is provided that includes a static random-access memory (SRAM) cell having Q and QB nodes and a non-volatile memory (NVM) array having a plurality of NVM cells. Each NVM cell comprises a memory element and a selector. The memory cell also includes select gates that selectively couple at least one of the Q and QB nodes to the plurality of NVM cells.

公开(公告)号：US08917551B2

公开(公告)日：2014-12-23

申请号：US13347913

申请日：2012-01-11

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/0441 ,  G11C16/10

摘要： A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0.

摘要翻译： 公开了一种用于PLD，PAL和匹配功能的NAND阵列的基于NVM的2T或2nT NAND单元。 优选的NVM单元可以是ROM或Flash。 2T闪存单元优选地使用FN进行编程和擦除操作，而2T ROM单元优选地将磷用于ROM代码注入来获得负Vt0。

公开(公告)号：US08809148B2

公开(公告)日：2014-08-19

申请号：US13200142

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/7883

摘要： A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

摘要翻译： 非易失性存储器件具有FLOTOX EEPROM非易失性存储器阵列的组合。 每个基于FLOTOX的非易失性存储器阵列由基于FLOTOX的非易失性存储器单元形成，其包括至少一个浮置栅极隧穿氧化物晶体管，使得控制栅极与浮置栅极隧道氧化物晶体管的浮置栅极的耦合比率约为60 ％至约70％，并且将浮置栅极与漏极区域的浮动栅极氧化物晶体管的耦合比保持为约10％至约20％的常数，并且使得沟道区的沟道长度为 减小，使得在编程过程期间将负编程电压电平施加到控制栅极，并且向漏极区域施加中等的正编程电压电平，以防止中等正编程电压电平超过漏源至源极击穿电压。

公开(公告)号：US08775719B2

公开(公告)日：2014-07-08

申请号：US12807996

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US08331150B2

公开(公告)日：2012-12-11

申请号：US12319241

申请日：2009-01-05

申请人： Fu-Chang Hsu ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Peter Wung Lee

IPC分类号： G11C14/00

CPC分类号： G11C14/00 ,  G11C14/0063 ,  Y10T29/49002

摘要： A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).

摘要翻译： 非易失性SRAM电路具有连接到SRAM单元的数据存储端的SRAM单元和一个或两个FLOTOX EEPROM单元。 在编程到第一数据电平时，FLOTOX EEPROM晶体管的阈值电压达到大于读取电压电平并被擦除到第二数据电平的编程电压电平，FLOTOX EEPROM晶体管的阈值电压被擦除 电压电平小于读取电压电平。 非易失性SRAM阵列用于在功率发生时从FLOTOX EEPROM存储单元向SRAM单元恢复数据，并在断电时将数据存储到SRAM单元中的FLOTOX EEPROM存储单元。 一种功率检测电路，用于提供指示功率启动和功率终止的信号，以在SRAM单元和FLOTOX EEPROM单元之间启动数据的恢复和存储。